Frame synchronizing signal generating circuit

Abstract

Abstract PURPOSE:To obtain a frame synchronizing signal generating circuit without generating a frame synchronizing signal in a shorter than a normal period by adopting the constitution such that a line counter is not reset till a line clock number does not reach a prescribed number. CONSTITUTION:A line counter 1 counts a line clock LCLK fed for each line of a picture signal, outputs a value (line number) CNT-Q and a decoder 2 outputs a frame synchronizing signal FRM when the line number CNT-Q reaches 0. A comparator circuit 3 compares the line number CNT-Q with a predetermined comparison number (in this case, 523) given via a comparison number input terminal 14 and gives a reset inhibit signal INH of logical 0 to an AND gate 4 while the line number CNT-Q is within 0-523. Thus, the AND gate 4 is opened and even when a frame pulse FP is inputted during this time, the line counter 1 is not reset. Thus, no frame synchronizing signal is generated in a shorter than normal period.

Inventors

• 👤 Yukio Endo
• 👤 幸男 遠藤
• 👤 Hatsuki Kawamata
• 👤 川股　初己
• 👤 Takuya Nohara
• 👤 野原　琢也

Bibliographic Details