Arithmetic unit for multiplication remainder

Abstract

Abstract PURPOSE:To reduce the circuit scale and to vary the calculating speed of the multiplication remainder by repeating the partial products calculation and adding the remainder result of the partial product to that of the next stage. CONSTITUTION:A multiplication circuit 1 is provided together with a remainder table 2, a 1st adder 3, a shift means 4, a 2nd adder 5, and a correction circuit 6. When the multiplication is carried out, all types of multiplication are not carried out and partial products divided into (m) times are calculated in the order of higher places. Then a remainder table is referred to with the bits flowed over the bit width of a processing unit set for the partial product. Thus the remainder of the partial product is calculated, and the result of this calculation is added to the partial product of the next stage. Then the remainder of the partial product addition is obtained with the overflowed bits of the addition result. Thus the scales of a multiplication circuit and the remainder table are reduced instead of increasing the calculation frequency. Furthermore the width of multiplication can be increased with extension of the partial product width.

Inventors

• 👤 Takayuki Hasebe
• 👤 高行 長谷部
• 👤 Naoya Torii
• 👤 直哉 鳥居
• 👤 Ryota Akiyama
• 👤 良太 秋山

Bibliographic Details