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JPH03215834A Expired / Lapsed JP ⏱️ 0.0 years remaining

Active matrix substrate

Assignee: Sharp Corp
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Filing: 1990-01-19
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Granted: —
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Expires: 2010-01-19
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Abstract

Abstract PURPOSE:To decrease the signal delay on additive capacity wirings and to obtain the display device having a high image grade by electrically connecting the adjacent additive capacity wirings to each other and taking out leader wires from the junctures at both ends of the respective additive capacity wirings. CONSTITUTION:The additive capacity wirings 2 are formed between gate bus wirings 1a and 1b. The additive capacity wirings 2 adjacent to each other are connected on the side where leader wires 21a and 21b of the gate bus wirings 1a and 1b positioned therebetween are not provided. The leader wires 22 and 22b are led out of the junctures thereof and terminals 12a and 12b for the additive capacities of the width larger than the leader wires 22a and 22b are provided at the terminals thereof. The signals corresponding to the video signals impressed to picture element electrodes are supplied through common wirings 3a and 3b of the additive capacities from both ends of the additive capacity wirings 2 and, therefore, the signal delay wirings on the additive capacity wirings 2 are decreased.

Inventors

  • 👤 Tadanori Hishida
  • 👤 忠則 菱田
  • 👤 Hirohisa Tanaka
  • 👤 田仲 広久

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-05 18:06
CPC Classifications
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