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JPH03212901A Expired / Lapsed JP ⏱️ 0.0 years remaining

Square board type chip resistor

Assignee: Panasonic Holdings Corp
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Filing: 1990-01-18
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Granted: —
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Expires: 2010-01-18
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Abstract

Abstract PURPOSE:To reduce irregularities of a glass surface and to realize high precision of packaging without increasing dispersion of resistance values and deteriorating oxide resistance of glass by providing a specified three layer glass layer of specified softening point and linear expansion coefficient on a thick film resistance layer. CONSTITUTION:An upper surface electrode 2 is formed on 96 alumina substrate 1 and a thick film resistance layer 4 mainly composed of RuO2 is formed partially overlapping thereon. A first glass layer 5 is formed thereon, whose glass softening point is 550 to 570 deg.C and linear expansion coefficient is 69X10<-7> to 7<5>X10<-7>/ deg.C. An imprinting glass layer 6 having a softening point of 550 to 570 deg.C and linear expansion coefficient of 68X10<-7> to 74X10<-7>/ deg.C and a second glass layer 7 having a softening point of 580 to 630 deg.C and linear expansion coefficient of 62X10<-7> to 68X10<-7>/ deg.C are formed thereon. An edge surface electrode layer 3 is formed, which partially overlaps with the layer 7 and the electrode layer 2. Since a softening point of the first glass layer 5 is lower than that of the second glass layer 7, the imprinting glass layer 6 sinks to the layer 5 and irregularities of a surface reduce, thereby preventing development of cracks on the surface.

Inventors

  • 👤 Masato Hashimoto
  • 👤 正人 橋本
  • 👤 Yoshiyuki Kita
  • 👤 喜多 吉幸

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-08 17:12
CPC Classifications
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