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JPH0314218A Expired / Lapsed JP ⏱️ 0.0 years remaining

Charged beam lithography

Assignee: Toshiba Corp
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Filing: 1989-06-13
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Granted: —
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Expires: 2009-06-13
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Abstract

Abstract PURPOSE:To make the acceleration of the data conversion time as well as the reduction of transfer data feasible while bringing together well compressed lithographic pattern data by a method wherein the positional data on common regions and local regions contained in frame regions as well as the figure data contained in the local regions are collected to bring together into the frame data. CONSTITUTION:In the title drawing method, an LSI chip region 1 is divided into three assumptive frame regions 51-53; a multitude of block regions defined by block data exist in the LSI chip region 1; and the block regions 3, 4, 7, 8 existing in the frame regions 51-53 are assumed to be common regions while the block regions 5, 6, 9 outside the common regions are assumed to be local regions. On the other hand, the positional data on the common regions and the local regions contained in the frame regions 51-53 as well as the frame data contained in the local regions are collected to bring together the frame data as the lithographic pattern data pertaining to one frame region so that the lithographic pattern data on the whole LSI chips may be composed of the set of frame data and the common data as the figure data on the common regions.

Inventors

  • 👤 Osamu Ikenaga
  • 👤 修 池永
  • 👤 Kiyomi Koyama
  • 👤 清美 小山
  • 👤 Ryoichi Yoshikawa
  • 👤 良一 吉川

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-03 14:42
CPC Classifications
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