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JPH0247849A Expired / Lapsed JP ⏱️ 0.0 years remaining

Semiconductor device

Assignee: NEC Corp
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Filing: 1988-08-10
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Granted: —
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Expires: 2008-08-10
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Abstract

Abstract PURPOSE:To prevent deterioration of characteristics so as to facilitate design by equipping it with a gate insulating film and a gate electrode which are formed at a defined element region, and source and drain regions which are formed at a semiconductor substrate by a self-alignment method making use of this gate electrode and a wiring film. CONSTITUTION:Since the insulation isolation at a MOSFET region is composed of a P-type diffusion layer 3 as substrate contact and an N-type diffusion layer 4 as well contact, there is no necessity of providing a thick oxide film by a selective oxidation method, thus high temperature treatment to a silicon substrate 1 can be avoided. Hereby, generation of lattice defect is prevented, and electric characteristics of a MOSFET formed is improved. Also, since power source VSS wiring 5 and power source VDD wiring 6 respectively in contact with a substrate contact 3 and a well contact 4 are formed in close contact with the silicon substrate at the region excepting the MOSFET region, that is, over the whole race of the insulation isolation region, the wiring area can be enlarged, and the resistance value can be reduced, and also they turn out to be formed in different layers from that or wiring for various kinds of signals, which facilitates the layout design of wiring for various kinds of signals.

Inventors

  • 👤 Toru Kume
  • 👤 徹 久米

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-10-29 08:56
CPC Classifications
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