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JPH0247731A Expired / Lapsed JP ⏱️ 0.0 years remaining

Dual comparator

Assignee: NEC Corp
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Filing: 1988-08-09
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Granted: —
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Expires: 2008-08-09
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Abstract

Abstract PURPOSE:To restart the dual comparison mode at the time of bracketing a faulty processor and at the time of interrupted trouble by executing a diagnostic program in each processor at the time of the occurrence of dual comparison error. CONSTITUTION:A diagnosing processor 10 operates a processor 20 in the dual comparison execution mode in accordance with a dual comparison mode indicating signal on a signal line 60 and a dual comparison execution mode signal on a signal line 40 and operates a processor 30 in the monitor mode in accordance with a comparison monitor mode signal on the signal line 40. A dual comparison error signal is transmitted from the processor 30 to the diagnosing processor 10 to cause the dual comparison error. Then, the diagnosing processor 10 resets the dual comparison mode signal on the signal line 60 to release the dual comparison mode. When a dual comparison error diagnosis indicating signal 120 becomes true, the diagnostic program is started for the processor 20.

Inventors

  • 👤 Tsuneo Suzuki
  • 👤 鈴木 経男
  • 👤 Hiroyuki Eguchi
  • 👤 江口 裕之

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-02 16:07
CPC Classifications
—

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