Semiconductor input protective circuit

Abstract

Abstract PURPOSE:To eliminate a trouble that a MOS transistor is destroyed in a state that a power-supply potential is not applied by a method wherein a pad and an internal gate are connected by the MOS transistor. CONSTITUTION:A pad 7 and an internal gate 8 are connected by an analog switch composed of a P-channel type MOS transistor QP and an N-channel type MOS transistor QN which are used as a pair. That is, in a state a power supply is not applied to an IC, a power-supply potential is not applied to gate electrodes of the P-channel type MOS transistor QP and the N-channel type MOS transistor QN. Accordingly, the analog switch is in an OFF state; the pad 7 and the internal gate 8 are in an electrically insulated state. When a high voltage is applied to the pad 7 by generation of static electricity or the like and an abnormal current is generated at this time, a parasitic P-N junction diode plays a role of a bypass against this abnormal potential. Thereby, even when the IC is transported or the like, a trouble that the MOS transistor constituting the internal gate 8 is destroyed is eliminated.

Inventors

• 👤 Yasunori Tanaka
• 👤 康規 田中

Bibliographic Details