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JPH0240924A Expired / Lapsed JP ⏱️ 0.0 years remaining

Manufacture of semiconductor device

Assignee: NEC Corp
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Filing: 1988-07-30
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Granted: —
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Expires: 2008-07-30
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Abstract

Abstract PURPOSE:To generate the structure of an offset in a self-alignment manner by a method wherein the thicknesses of sidewalls, which are generated on both sides of a gate electrode by anisotropic etching in the direction of inclination, are made to differ from each other, whereby these thicknesses are each set intact as the interval between a source and the gate electrode and the inverval between a drain and the gate electrode. CONSTITUTION:An n-type active layer 2 is formed in the surface layer part of a semi- insulative GaAs substrate 1 and a gate metal film 5, which is used as a Schottky junction and consists of a tungsten silicide, is provided on this layer 2. Then, a reactive dry etching is performed to turn the film 5 into a gate electrode 5A, the whole surface including this electrode 5A is covered with an SiO2 film (an Si oxide film) 6 and SiO2 films 6s and 6d are made to remain only on the sidewalls of the electrode 5A by performing an anisotropic etching using C4F8. Here, as the incident angle of ions is slanted on the side of a source to the substrate 1, the thickness of the sidewall 6s becomes thinner than that of the sidewall 6d. After that, ions are implanted using the electrode 5A and the sidewalls 6s and 6d as masks to form high-concentration carrier layers 4s and 4d, which are used as the source and a drain, on each side of both sidewalls and a large offset is grown between the layer 4d and the electrode 5A.

Inventors

  • 👤 Seiji Ichikawa
  • 👤 市川 清治

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-10-28 22:37
CPC Classifications
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