Manufacture of bipolar transistor

Abstract

Abstract PURPOSE:To obtain a dimension finner than a dimension, which is restricted by a lithography technique, and to reduce a junction capacitance by a method wherein an eroded part is formed utilizing a first sidewall provided on the inner side of an opening in an insulating film and with graft base regions provided by diffusing an impurity through this eroded part, a base region and an emitter region are formed utilizing a second sidewall. CONSTITUTION:An n<+> buried layer 2, is formed in a P-type Si substrate 1, an n-type layer 3 is epitaxially grown on the whole surface including this layer 2 and the layer 3 is partitioned by an SiO2 film 4 to use here as an element formation region. Then, an insulating film 5, a poly Si film 6, an n<+> collector lead-out layer 7 and insulating layers 8 and 9 are laminated on the whole surface of this element formation region, an opening is pored to expose the element formation region and here is covered with an insulating film 11. After that, an etching is performed to remove both end parts of the film 11 and at the same time, an eroded part 8a is made to generate in the sidewall of the opening and an impurity is diffused through this part 8a to form graft base regions 12 under the end parts of the lower surface of the film 11. Then, a treatment identical with the above treatment is performed, a P-type emitter region 19 is formed between the regions 12 and an n<+> active base region 16, which is positioned on the surface layer part of this region 19, is formed.

Inventors

• 👤 Tsutomu Akashi
• 👤 勉 明石

Bibliographic Details