Emitter coupled logic circuit

Abstract

Abstract PURPOSE:To cause a switching speed to be high-speed by connecting the collector of a transistor in a signal basic cell to compose plural current switches, respectively, in the signal basic cell. CONSTITUTION:In a basic cell 10B, the respective collectors of transistors Q1B and Q2B are connected by a first layer wiring 22. To respective terminals 11b and 12b, a reference voltage VBB is impressed, and an AND X.Y of signals X and Y inputted to the terminals 11a and 12a, respectively, is outputted through a transistor Q3B of an emitter follower from a terminal 13b. In such a way, since a collector connecting point is executed by the first layer wiring 22 in the basic cell 10B and the wiring 22 is sufficient by the degree of approximately 1/2 in comparison with a conventional case, the collector wiring capacities of the transistors Q1B and Q2B is are made small, and the switching speed can be made high-speed.

Inventors

• 👤 Hiroyuki Kadoi
• 👤 角井　広幸
• 👤 Eiji Sugiyama
• 👤 英治 杉山
• 👤 Naoyuki Ando
• 👤 安藤　直行
• 👤 Yasuhiko Tando
• 👤 丹藤　安彦
• 👤 Chikahiro Seto
• 👤 瀬戸　親寛

Bibliographic Details