Semiconductor integrated circuit device

Abstract

Abstract PURPOSE:To simultaneously actualize the high integration and the ultraacceleration by a method wherein a power supply system layer and a signal processing system layer are laminated through the intermediary of an insulating layer while a conductor passing through the insulating layer is provided to supply power supply voltage and reference bias voltage. CONSTITUTION:An insulating layer 20 is formed on a power supply layer 10 and then a silicon single crystal grown layer 31 is formed on the layer 20 by epitaxial growth, etc. Next, a groove 3 is formed around a transistor region 38 to be filled up with a polycrystalline silicon 4a and simultaneously a through hole passing through from the silicon single crystal grown layers 31 side to the insulating layer 20 reaching the power supply system layer 10 is formed to be filled up with another polycrystalline silicon 4b and then implanted with ions to form a conductor 2. Through these procedures, a signal processing system layer 30 is subjected to logic gate input-output wirings only by supplying power supply voltage and reference bias voltage from the power supply system layer 10 to the signal processing system layer 30 through the conductor 2. Consequently, when the logic gate is laid on any positions other than the arranged position of conductor 2, the logic gate size and the wiring region can be miniaturized, thereby cutting down the wirings between the logic gates.

Inventors

• 👤 Naoyuki Miyazawa
• 👤 宮沢　直行
• 👤 Kenji Hasegawa
• 👤 長谷川　堅二
• 👤 Rokutaro Ogawa
• 👤 禄太郎 小川

Bibliographic Details