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JPH023944A Expired / Lapsed JP ⏱️ 0.0 years remaining

Semiconductor device

Assignee: Mitsubishi Electric Corp
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Filing: 1988-06-20
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Granted: —
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Expires: 2008-06-20
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Abstract

Abstract PURPOSE:To reduce input capacitance by reducing the area of a polycrystalline silicon layer as compared with a bonding pad, forming said layer locally, and bringing said layer into contact only with a bonding pad. CONSTITUTION:A polycrystalline silicon layer 3a is locally formed only for a contact part 7, and its area is sufficiently small as compared with a bonding pad 5. In an insulating film 4, a hole 4a corresponding with the polycrystalline silicon layer 3a is opened, and the contact part 7 is formed by stretching a part of the aluminum pad 5 via the hole 4a. Thereby the minimum area of the polycrystalline silicon layer 3 can be realized.

Inventors

  • 👤 Shuji Murakami
  • 👤 修二 村上
  • 👤 Kenji Anami
  • 👤 穴見 健治

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-01 20:34
CPC Classifications
H; H10; H10W; H10W72/00; H10W72/90; H10W72/921; H10W72/923; H10W72/931; H10W72/932; H10W72/934; H10W72/951; H10W72/952; H10W72/981; H10W72/983

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