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JPH02106943A Expired / Lapsed JP ⏱️ 0.0 years remaining

Mounting structure of semiconductor integrated circuit

Assignee: NEC Corp
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Filing: 1988-10-17
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Granted: —
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Expires: 2008-10-17
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Abstract

Abstract PURPOSE:To inhibit a voltage drop by wiring resistance at a low value by conducting connection by a metallic lead bonded with a metallic protrusion through a thermocompression bonding method, etc., in the peripheral section of a VLSI chip and connection by a metallic protrusion formed at the central section of the VLSI chip. CONSTITUTION:There are two kinds of the connection of a peripheral section, in which metallic leads 4 bonded with metallic protrusions 2 shaped to the peripheral section of a VLSI chip through a thermocompression bonding method, etc., are cemented to metallic protrusions 6 formed onto a circuit board 7, and the connection of a central section, in which bumps 3 shaped at the central section of the VLSI chip 1 are connected to the metallic protrusions 6 of the circuit board 7 through solder 5, in the connection of the wirings of the VLSI chip 1 and the mounting wirings 9 of the circuit board 7. Both are jointed with the specified wirings of another VLSI chip 1 or predetermined external connecting pins 8 through the mounting wirings 9 of the surface of the circuit board 7 or internal mounting wirings 10.

Inventors

  • 👤 Teruo Kusaka
  • 👤 日下 輝雄

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-04 09:20
CPC Classifications
H; H10; H10W; H10W72/00; H10W72/701

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Total Claims: 0
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