Interruption generation circuit for debug

Abstract

Abstract PURPOSE:To efficiently make debugging by previously designating the address range of a functional routine to be verified in a microprogram and generating interruption when the designated address range is executed. CONSTITUTION:This interruption generation circuit is provided with a controlling storage 1, instruction register, execution controlling section 3, comparing address registers 5 and 6, comparator circuits 7 and 8, arithmetic circuit 9, and control circuit 10. By respectively storing necessary addresses in the comparing address registers 5 and 6 and designating a necessary mode to the control circuit 10, interruption is generated under the address range conditions of a microprogram and two-point address conditions. Therefore, a strong debugging means is obtained and the debugging efficiency can be improved.

Inventors

• 👤 Masaru Ito
• 👤 勝 伊藤

Bibliographic Details