Semiconductor integrated circuit device

Abstract

Abstract PURPOSE:To expand the amplitude of a complementary signal sent via a bipolar CMOS composite gate circuit up to a CMOS level by providing two CMOS inverter circuits whose input and output terminals are connected in crossing between output terminals of two bipolar CMOS composite gate circuits giving a couple of complementary output signals. CONSTITUTION:With a clock signal CK brought into a low level, a CMOS clocked inverter circuit CN1 is made nonconductive and a CMOS clocked inverter circuit CN2 is made conductive. Thus, a latch comprising a CMOS inverter circuit N3 and a CMOS clocked inverter circuit CN2 is kept in the data storage state. In this case, outputs signals of bipolar CMOS inverter circuits BN1, BN2, that is, a noninverting output signal Q and an inverting output signal Q invert said latch stored data respectively and become complementarily at a high level or a low level. The output signals are expanded to a CMOS level nearly a power voltage VCC and a power voltage VSS finally.

Inventors

• 👤 Tsukasa Ichinose
• 👤 市ノ瀬　吏

Bibliographic Details