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JPH0196952A Expired / Lapsed JP ⏱️ 0.0 years remaining

Hermetically sealed chip carrier

Assignee: Hitachi Ltd
•
Filing: 1987-10-09
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Granted: —
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Expires: 2007-10-09
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Abstract

Abstract PURPOSE:To obtain a hermetically sealed chip carrier having preferable thermal conductivity without loss of the hermetical sealability of the carrier due to the inclination of a semiconductor circuit chip or the irregularity in the thickness of a sealing member by placing the chip to which a heat sink stud is secured on a substrate to which a framelike member is secured, and filling sealing electrically insulating resin between the stud and the framelike member. CONSTITUTION:An integrated circuit chip 1 in which a heat sink stud 3 is secured in a cavitylike space formed by securing a framelike member 5 to a substrate 6 is connected through a solder terminal 4 to the substrate, and sealing electrically insulating resin 10 is so filled between the member 5 and the stud 3 as to completely cover the surfaces of the chip 1, the terminal 4 and the substrate 6. Further, in order to provide preferably hermetical sealability, the top of the resin is covered with low melting point metal 11. Then, the electric signal of the chip 1 is led through the terminal 4 and a through hole 8 to an exterior, and connected by a solder connecting section 7 to a circuit substrate 7. The heat generated in the chip 1 is externally led by the stud 3, and absorbed by a heat sink.

Inventors

  • 👤 Keiichiro Nakanishi
  • 👤 中西 敬一郎
  • 👤 Minoru Yamada
  • 👤 稔 山田

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-05 10:29
CPC Classifications
H; H10; H10W; H10W72/00; H10W72/071; H10W72/073; H10W72/07331; H10W74/00; H10W74/10; H10W74/15; H10W90/00; H10W90/701; H10W90/721; H10W90/724

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