JP3172362B2
Expired / Lapsed
JP
⏱️ 0.0 years remaining
Layout method of semiconductor integrated circuit
Assignee: 松下電子工業株式会社
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Filing: 1994-05-25
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Granted: 2001-06-04
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Expires: 2014-05-25
Abstract
No abstract record available.
Inventors
- 👤 田中 誠
- 👤 睦 大西
- 👤 裕子 光安
- 👤 尚生 野村
Bibliographic Details
Application Number
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Jurisdiction
JP
Data Source
google_patents
Last Synchronized
2026-10-26 06:57
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