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JP2004235586A Expired / Lapsed JP ⏱️ 0.0 years remaining

Semiconductor device

Assignee: Sony Corp
•
Filing: 2003-01-31
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Granted: —
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Expires: 2023-01-31
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Abstract

Abstract Translated from Japanese 【課題】ボンディングの荷重により低誘電率絶縁層内にクラック等の発生を防止して信頼性と特性の向上を図る。 【解決手段】多孔質性の低誘電率絶縁材からなる低誘電率絶縁層12内に微細化された銅配線パターン層10を多層に形成するとともに最上層にボディングパッド部6を形成してなる。ボンディングパッド部6に対応する内層部に、銅配線パターン層と同層に形成された保持配線パターン22と、これら保持配線パターン22を層間接続するようにして形成された保持プラグ層23とからなる保持銅パターン層15を形成してなる。 【選択図】 図1 An object of the present invention is to improve the reliability and characteristics by preventing the occurrence of cracks and the like in a low dielectric constant insulating layer due to a bonding load. A fine copper wiring pattern layer is formed in multiple layers in a low dielectric constant insulating layer made of a porous low dielectric constant insulating material, and a boding pad portion is formed in an uppermost layer. Become. In an inner layer portion corresponding to the bonding pad portion 6, a holding wiring pattern 22 formed in the same layer as the copper wiring pattern layer and a holding plug layer 23 formed so as to connect the holding wiring patterns 22 to each other are provided. The holding copper pattern layer 15 is formed. [Selection diagram] Fig. 1

Inventors

  • 👤 Kazuo Nishiyama
  • 👤 和夫 西山

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-02 06:03
CPC Classifications
H; H10; H10W; H10W72/00; H10W72/90; H10W72/50; H10W72/531; H10W72/536; H10W72/59; H10W72/921; H10W72/923; H10W72/9232; H10W72/931; H10W72/932; H10W72/981; H10W72/983

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