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JP2002131389A Expired / Lapsed JP ⏱️ 0.0 years remaining

Semiconductor integrated circuit device

Assignee: Hitachi Ltd
•
Filing: 2000-10-30
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Granted: —
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Expires: 2020-10-30
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Abstract

Abstract PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device realizing a plurality of kinds of action verification for a clock generation circuit forming an internal clock signal and allowing verification for various kinds of performance of the internal clock signal generation circuit to be carried out while simplifying the structure. SOLUTION: In the clock generation circuit forming the internal clock signal made to correspond to an input clock signal inputted from an external terminal, a measurement circuit performing at least two measurements among a measurement of a lock time required for obtaining a desired internal clock signal matching the input clock signal, a measurement of a maximum frequency for the internal clock signal, and a measurement of jitter in the internal clock signal is arranged, and consequently, operation of the clock generation circuit is verified with high precision inside the semiconductor integrated circuit.

Inventors

  • 👤 Takashi Matsumoto
  • 👤 隆 松本
  • 👤 Hikari Suzuki
  • 👤 光 鈴木
  • 👤 Mitsugi Kusunoki
  • 👤 貢 楠

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-10-29 10:04
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/31708; G01R31/31709; G01R31/31725; G11; G11C; G11C29/00; G11C29/04; G11C29/08; G11C29/12; G11C29/14; H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/081; H03L7/0812; H03L7/0814; H03L7/0816; H03L7/085; H03L7/095; H03K; H03K5/00; H03K2005/00013; H03K2005/00019; H03K2005/00058; Y; Y10; Y10S; Y10S331/00; Y10S331/02

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