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JP2001044591A Expired / Lapsed JP ⏱️ 0.0 years remaining

Wiring board

Assignee: Niterra Co Ltd
•
Filing: 1999-08-03
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Granted: —
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Expires: 2019-08-03
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Abstract

Abstract Translated from Japanese (57)【要約】 【課題】 電源電位や接地電位などに接続する多数のビ アについて、そのインダクタンスを低減した配線基板を 提供すること。 【解決手段】 ICチップCHを搭載するための本発明 の配線基板100は、樹脂絶縁層103〜105をそれ ぞれ貫通して形成され、電源電位に接続されてICチッ プCHへ供給する電流の往路となる多数の電源ビア13 1、及び、接地電位に接続されて上記電流の復路となる 多数の接地ビアとを備える。電源ビア131同士は互い に格子状に配置され、接地ビア141同士は互いに格子 状に配置されている。しかも、電源ビア131と接地ビ ア141とは、それぞれ互いの格子の目に配置されてい る。 (57) [Problem] To provide a wiring board with reduced inductance for a large number of vias connected to a power supply potential, a ground potential, and the like. SOLUTION: A wiring board 100 of the present invention for mounting an IC chip CH is formed so as to penetrate through resin insulating layers 103 to 105, respectively, is connected to a power supply potential, and is provided with a forward path of a current supplied to the IC chip CH. Many power supply vias 13 1, and a number of ground vias connected to the ground potential and serving as a return path for the current. The power supply vias 131 are arranged in a grid pattern, and the ground vias 141 are arranged in a grid pattern. In addition, the power supply via 131 and the ground via 141 are arranged in the grid of each other.

Inventors

  • 👤 Koju Ogawa
  • 👤 幸樹 小川
  • 👤 Eiji Kodera
  • 👤 英司 小寺

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-09 11:48
CPC Classifications
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