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JP2000332124A Expired / Lapsed JP ⏱️ 0.0 years remaining

Semiconductor device

Assignee: Toshiba Corp
•
Filing: 1999-09-30
•
Granted: —
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Expires: 2019-09-30
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Abstract

Abstract Translated from Japanese (57)【要約】 【課題】 接合温度が上昇することによって引き起こさ れる効率の劣化を防ぐ。 【解決手段】 電力増幅用のトランジスタとカレントミ ラー回路のトランジスタ6を金属電極層4で熱的に結合 するか、カレントミラー回路の電位生成用トランジスタ を電力増幅用トランジスタのフィンガー1A,1B間に 配するか、カレントミラー回路の電位生成用トランジス タと電力増幅用トランジスタのフィンガー1A,1B間 の距離を半導体基板7厚よりも縮小するかのいずれかの 手段を用いる。 (57) [Summary] [PROBLEMS] To prevent deterioration in efficiency caused by an increase in junction temperature. SOLUTION: A power amplification transistor and a transistor 6 of a current mirror circuit are thermally coupled with a metal electrode layer 4, or a potential generation transistor of a current mirror circuit is arranged between fingers 1A and 1B of the power amplification transistor. Or the distance between the potential generating transistor of the current mirror circuit and the fingers 1A and 1B of the power amplifying transistor is made smaller than the thickness of the semiconductor substrate 7.

Inventors

  • 👤 Kohei Moritsuka
  • 👤 宏平 森塚
  • 👤 Yasuhiko Kuriyama
  • 👤 保彦 栗山

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-09 16:55
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/60; H10D84/645; H03; H03F; H03F1/00; H03F1/02; H03F1/0205; H03F1/0261; H03F1/30; H03F1/302; H03F3/00; H03F3/189; H03F3/19

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