GB2049202A
Expired / Lapsed
GB
⏱️ 0.0 years remaining
Eprom reliability test circuit
Assignee: Fairchild Semiconductor Corp
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Filing: 1980-02-26
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Granted: —
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Expires: 2000-02-26
Abstract
No abstract record available.
Inventors
No inventors recorded.
Bibliographic Details
Application Number
—
Jurisdiction
GB
Data Source
google_patents
Last Synchronized
2026-10-23 02:57
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/04; G11C29/50; G11C29/50004; G11C29/50016; G06; G06F; G06F2201/00; G06F2201/81; G11C16/00; G11C16/02; G11C16/04
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
134 words
Test circuitry for enabling the measurement of the read signal threshold voltage necessary to produce a readout of a selected EPROM matrix memory cell common to one of a plurality of cell enabling lines and one of a plurality of cell read signal lines, said circuit including: first input means for receiving a test voltage at a level higher than the threshold level of any cell in the matrix; second input means for receiving a measurable externally generated slide voltage variable between levels higher and lower than the threshold voltage of any cell in said matrix; and a voltage control transistor coupled to said first input means, said second input means, and each of the cell read signal lines in said matrix for transferring said measurable slide voltage to its respective read signal line.
Claim 2
Dependent Claim
134 words
Test circuitry for enabling the measurement of the read signal threshold voltage necessary to produce a readout of a selected EPROM matrix memory cell common to one of a plurality of cell enabling lines and one of a plurality of cell read signal lines, said circuit including: first input means for receiving a test voltage at a level higher than the threshold level of any cell in the matrix; second input means for receiving a measurable externally generated slide voltage variable between levels higher and lower than the threshold voltage of any cell in said matrix; and a voltage control transistor coupled to said first input means, said second input means, and each of the cell read signal lines in said matrix for transferring said measurable slide voltage to its respective read signal line.
Claim 3
Dependent Claim
29 words
The circuitry claimed in Claim 1 wherein said EPROM is a MOS integrated circuit and wherein said test circuitry is formed on the same IC chip with said EPROM.
Claim 4
Dependent Claim
46 words
The test circuitry claimed in Claim 2 wherein said voltage control transistor is an enchancement transistor having its source and drain electrodes respectively coupled to said first input means and said read signal line, the gate of said transistor being coupled to said second input means.
Claim 5
Dependent Claim
65 words
The test circuitry claimed in Claim 2 wherein said voltage control transistor is an enchancement transistor having its source and drain electrodes respectively coupled to said second input means and said read signal line, the gate of said transistor being coupled to said first input means for transferring to said read signal line a voltage equal to the voltage applied to said second input means.
Claim 6
Dependent Claim
20 words
The test circuitry claimed in Claim 3 further including third input means for receiv- ing a test circuitry enabling signal.
Claim 7
Dependent Claim
39 words
The test circuitry claimed in Claim 5 wherein the conductor coupling said enhancement transistor with said first input means includes a normally non-conductive series switching transistor, that is rendered conductive by the application of said test circuit enabling signal.
Claim 8
Dependent Claim
62 words
The test circuitry claimed in Claim 6 wherein said third input means includes trans- istor circuitry responsive to the application of said test circuit enabling signal for disconnecting the control gate of said series switching transistor from ground reference potential and coupling said gate to said first input means for rendering said switching transistor fully 4 GB 2 049 202A 4 conductive.
Claim 9
Dependent Claim
47 words
Test circuitry substantially as herein described with reference to the accompanying drawing. Printed for Her Majesty's Stationery Office by Burgess & Son (Abingdon). Ltd.-1 980. Published at The Patent Office, 25 Southampton Buildings, Lon8on', WC2A 1AY, from which copies may be obtained. t X i 1 r
Claim 10
Dependent Claim
47 words
Test circuitry substantially as herein described with reference to the accompanying drawing. Printed for Her Majesty's Stationery Office by Burgess & Son (Abingdon). Ltd.-1 980. Published at The Patent Office, 25 Southampton Buildings, Lon8on', WC2A 1AY, from which copies may be obtained. t X i 1 r
References Cited (Backward Citations)
No citation records indexed.
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