GB2042296A
Expired / Lapsed
GB
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Nonvolatile static random access method and memory device
Assignee: Xicor LLC
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Filing: 1980-01-16
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Granted: —
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Expires: 2000-01-16
Abstract
Abstract Nonvolatile, semiconductor random access memory cells comprising a static, RAM cell and a nonvolatile memory element which may be interconnected with the static random-access memory cell by capacitative coupling, such that the RAM cell contents may be directly copied to the nonvolatile element, and such that the nonvolatile memory cell contents will be copied to the RAM cell upon applying power to the RAM cell. The nonvolatile memory element may be a substrate-coupled floating gate cell incorporating self-regulated and asperity enhanced tunnel currents. <IMAGE>
Inventors
No inventors recorded.
Bibliographic Details
Application Number
—
Jurisdiction
GB
Data Source
google_patents
Last Synchronized
2026-10-23 07:04
CPC Classifications
G; G11; G11C; G11C14/00; G11C11/00; G11C11/21; G11C11/34; G11C11/40; H; H10; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/681; H10D30/683
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
138 words
A nonvolatile memory device comprising a volatile semiconductor memory cell for storing binary data, means for reading from and writing to said volatile memory cell, a nonvolatile memory means, comprising an electrically insulated floating gate conductor, for storing binary data as one of two different electric charge levels on said floating gate conductor, means for capacitively coupling said volatile memory cell to said nonvolatile memory means and for copying the memory state of said bistable memory cell to the floating gate component as a predetermined one of said electric charge levels floating gate conductor, and means for capacitively coupling said floating gate conductor of said nonvolatile memory means to the said volatile memory cell for copying the memory state of said floating gate to said volatile memory cell upon application of electrical power to said volatile memory cell.
Claim 2
Dependent Claim
138 words
A nonvolatile memory device comprising a volatile semiconductor memory cell for storing binary data, means for reading from and writing to said volatile memory cell, a nonvolatile memory means, comprising an electrically insulated floating gate conductor, for storing binary data as one of two different electric charge levels on said floating gate conductor, means for capacitively coupling said volatile memory cell to said nonvolatile memory means and for copying the memory state of said bistable memory cell to the floating gate component as a predetermined one of said electric charge levels floating gate conductor, and means for capacitively coupling said floating gate conductor of said nonvolatile memory means to the said volatile memory cell for copying the memory state of said floating gate to said volatile memory cell upon application of electrical power to said volatile memory cell.
Claim 3
Dependent Claim
18 words
The cell of Claim 1 in which the volatile memory cell is a bistable cross-coupled flip-flop memory cell.
Claim 4
Dependent Claim
18 words
The cell of Claim 1 in which the memory cell is a six-transistor n-channel static random-access memory cell.
Claim 5
Dependent Claim
18 words
The cell of Claim 1 in which the memory cell is a four-transistor n-channel static random-access memory cell.
Claim 6
Dependent Claim
20 words
A cell in accordance with Claim 1 in which said memory cell is a six-transistor CMOS/SOS static random-access memory cell.
Claim 7
Dependent Claim
19 words
The cell of Claim 1 in which said memory cell is a six-transistor bulk CMOS static random-access memory cell.
Claim 8
Dependent Claim
17 words
A cell in accordance with Claim 1 wherein said volatile memory cell is a dynamic memory cell.
Claim 9
Dependent Claim
36 words
A cell in accordance with Claim 1 wherein the nonvolatile memory means comprises a plurality of electrodes and wherein at least two of said electrodes and said floating gate are constructed with three layers of polysilicon.
Claim 10
Dependent Claim
28 words
A cell in accordance with Claim 1 wherein asperities are provided to promote electron flow to and from said floating gate conductor component of said nonvolatile memory means.
Claim 11
Dependent Claim
35 words
A cell in accordance with Claim 1 wherein application of a single "store" voltage control signal to the cell causes the contents of said volatile memory cell to be transferred into said nonvolatile memory means.
Claim 12
Dependent Claim
17 words
A cell in accordance with Claim 1 in integrated circuit array with a plurality of like cells.
Claim 13
Independent Claim
110 words
A method for nonvolatile storage of binary information in a semiconductor integrated circuit, comprising the steps of capacitively sensing the one of two binary memory states of a volatile semiconductor memory cell having binary information stored therein, providing a predetermined one of two electric charge levels on a dielectrically isolated floating gate conductor corresponding to said one capacitively sensed memory state of said volatile memory cell without altering the memory state of said volatile memory cell, subsequently capacitively sensing said one of two charge levels of said floating gate conductor, and providing said volatile memory cell with the same said one of two memory states corresponding to said gate conductor.
Claim 14
Independent Claim
110 words
A method for nonvolatile storage of binary information in a semiconductor integrated circuit, comprising the steps of capacitively sensing the one of two binary memory states of a volatile semiconductor memory cell having binary information stored therein, providing a predetermined one of two electric charge levels on a dielectrically isolated floating gate conductor corresponding to said one capacitively sensed memory state of said volatile memory cell without altering the memory state of said volatile memory cell, subsequently capacitively sensing said one of two charge levels of said floating gate conductor, and providing said volatile memory cell with the same said one of two memory states corresponding to said gate conductor.
References Cited (Backward Citations)
No citation records indexed.
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