Power transistor device with controlled common lead inductance

Claim 2

1 A high frequency transistor device including a transistor chip having emitter, base and collector areas, a thermally con 70 ducting electrically insulating substrate member on which the transistor chip is mounted, input conductor means mounted on said substrate member and connected to one of said base and collector areas, output 75 conductor means mounted on said insulating substrate and connected to the other of said base and collector areas, said input and output conductor means being essentially in line with each other, a relatively large area 80 input ground lead conductor means mounted on said substrate, a relatively large area output ground lead conductor means mounted on said substrate, said input ground lead conductor means and said output 85 ground lead conductor means having input portions and output portions essentially in line with each other and parallel to said input and said output conductor means, and at least two wire 90 leads extending from said emitter area to separate points on said input and output ground lead conductor means respectively, means for controlling the common lead inductance from said emitter area to said in 95 put and output ground lead conductor means comprising a gap between said input and output ground lead conductor means between said separate points.

Claim 3

2 A high frequency transistor device as 100 claimed in Claim 1 wherein the means for controlling said common lead inductance includes one or more wire leads extending across said gap.

Claim 4

3 A high frequency transistor as claimed 105 in Claim 2 wherein the large area lead conductors on each side of said gap include lateral extensions, and said one or more wire leads extend across said gap to said extensions 110

Claim 5

4 A high frequency transistor device comprising a thermally conducting and electrically insulating supporting structure, metallized areas insulated from each other disposed, on said supporting structure, a 115 transistor chip having emitter areas, base areas and a collector bonded to one of said metallized areas, spaced apart and inner end connected large area input ground conductors bonded at their connected inner ends to 120 a second metallized area, spaced apart and.

Claim 6

4 A high frequency transistor device comprising a thermally conducting and electrically insulating supporting structure, metallized areas insulated from each other disposed, on said supporting structure, a 115 transistor chip having emitter areas, base areas and a collector bonded to one of said metallized areas, spaced apart and inner end connected large area input ground conductors bonded at their connected inner ends to 120 a second metallized area, spaced apart and.

Claim 7

inner end connected large area output ground conductors bonded at their connected inner ends to a third metallized area, a large area input conductor disposed between 125 the spaced apart portions of said input ground conductors and bonded to a fourth one of said metallized areas, a large area output conductor disposed between the spaced apart portions of said output ground 130 1 574 497 1 574 497 conductors and bonded to a fifth one of said metallized areas, a capacitor having a ground plate and a second plate, the ground plate of which is bonded to the inner end connection of said input ground conductors, wire leads of substantially equal length bonded to said emitter area and to the inner end connections of said input and said output ground leads respectively, wire leads bonded to said base area and said second plate of said capacitor, wire leads bonded to said second plate of said capacitor and to said input conductor, wire leads bonded to the collector metallized area and said output conductor, the opposed ends of said input and output ground conductors adjacent the said inner connected ends being spaced apart from each other and forming a gap between the opposed ends, and means for controlling the inductance of said leads connected to said emitter areas and said input and output ground conductors comprising one or more wire leads extending across said gaps and bonded to the opposed ends of said inner and, outer ground conductors. A high frequency transistor device as claimed in Claim 4 wherein the spaced apart inner ends of said input and output ground leads include extensions lateral to said ground leads, said gaps being disposed between said extensions, and said one or more wire leads extend across said gaps to said extensions.

Claim 8

6 A high frequency transistor device as claimed in Claim 5 wherein there are four lateral extensions, one from each of input and output ground conductors.

Claim 9

7 A high frequency transistor package as claimed in Claim 6 wherein said four lateral extensions define two pairs of extensions of equal length.

Claim 10

8 A high frequency transistor device as claimed in Claim 6 wherein the lengths of said extensions is determined and the position of said leads across said gaps is determined to provide a predetermined value of common emitter lead inductance.

Claim 11

9 A high frequency transistor device as claimed in Claim 4 wherein the transistor 50 chip includes several emitter areas, and a corresponding number of base areas, and said capacitor is an MOS capacitor.

Claim 12

A high frequency semiconductive device having at least one active region, and a 55 thermally conducting and electrically insulating substrate on which said semiconductive device is mounted, input conductor means mounted on said insulating substrate, output conductor means mounted on said insulating 60 substrate, said input and said output conductor means being essentially in line with each other, large area input ground lead conductor means mounted on said substrate, large area output ground lead conductor 65 means mounted on said substrate, said input ground lead conductor means and said output ground lead conductor means having input portions and output portions essentially in line with each other and parallel to 70 said input and said output conductor means, and at least two wire leads extending from the same point on said active region to separate points respectively on said input and output ground lead conductor means, 75 means for controlling the common lead inductance from said point on said active area to said input and output ground lead conductor means comprising a gap between said input and output ground lead conductor 80 means between said separate points.

Claim 13

A high frequency semiconductive device having at least one active region, and a 55 thermally conducting and electrically insulating substrate on which said semiconductive device is mounted, input conductor means mounted on said insulating substrate, output conductor means mounted on said insulating 60 substrate, said input and said output conductor means being essentially in line with each other, large area input ground lead conductor means mounted on said substrate, large area output ground lead conductor 65 means mounted on said substrate, said input ground lead conductor means and said output ground lead conductor means having input portions and output portions essentially in line with each other and parallel to 70 said input and said output conductor means, and at least two wire leads extending from the same point on said active region to separate points respectively on said input and output ground lead conductor means, 75 means for controlling the common lead inductance from said point on said active area to said input and output ground lead conductor means comprising a gap between said input and output ground lead conductor 80 means between said separate points.

Claim 14

11 A high frequency semiconductive device as claimed in Claim 10 wherein the means for controlling said common lead inductance includes one or more wire leads 85 extending across said gaps.

Claim 15

12 A high frequency transistor device substantially as hereinbefore described and as shown in the accompanying drawing. For the Applicants:F J CLEVELAND & COMPANY, Chartered Patent Agents, Lincoln's Inn Chambers, 40-43 Chancery Lane, London, WC 2 A 1 JQ. Printed for Her Majesty's Stationery Office by The Tweeddale Press Ltd, Berwick-upon-Tweed, 1980. Published at the Patent Office, 25 Southampton Buildings, London, Wc 2 A l AY, from which copies may be obtained.

Claim 16

12 A high frequency transistor device substantially as hereinbefore described and as shown in the accompanying drawing. For the Applicants:F J CLEVELAND & COMPANY, Chartered Patent Agents, Lincoln's Inn Chambers, 40-43 Chancery Lane, London, WC 2 A 1 JQ. Printed for Her Majesty's Stationery Office by The Tweeddale Press Ltd, Berwick-upon-Tweed, 1980. Published at the Patent Office, 25 Southampton Buildings, London, Wc 2 A l AY, from which copies may be obtained.