INPUT PROTECTION FOR INTEGRATED MOS CIRCUIT AT LOW SUPPLY VOLTAGE AND HIGH INTEGRATION DENSITY

Abstract

Abstract Translated from French PROTECTION D'ENTREE CONTRE LES SURTENSIONS ACCIDENTELLES POUR DES DISPOSITIFS A CIRCUIT INTEGRE DE TYPE MOS A BASSE TENSION D'ALIMENTATION ET A FORTE DENSITE D'INTEGRATION, COMPRENANT DES IGFET (TRANSISTORS A EFFET DE CHAMP A GACHETTE ISOLEE) DONT LES OXYDES DE GACHETTE ONT UNE EPAISSEUR QUI NE DEPASSE PAS 500A. ELLE EST CONSTITUEE ESSENTIELLEMENT PAR UN TRANSISTOR BIPOLAIRE LATERAL T DONT L'EMETTEUR EST RACCORDE A LA MASSE ET LE COLLECTEUR EST RACCORDE A L'ENTREE I ET AUX ELECTRODES G DE GACHETTE DES IGFET M. LA REGION DE BASE EST FORTEMENT DOPEE PAR IMPLANTATION IONIQUE D'IMPURETES DONT LA CONCENTRATION EST SUPERIEURE A CELLE DES AUTRES REGIONS DU CIRCUIT INTEGRE AYANT LA MEME POLARITE. DE CETTE MANIERE, LA TENSION DE CLAQUAGE AU NIVEAU DE LA PROTECTION EST INFERIEURE A LA TENSION DE CLAQUAGE AU NIVEAU DU RESTE DE CIRCUIT: LES OXYDES MINCES DE GACHETTE SONT PROTEGES CONTRE LA RUPTURE SANS EFFETS SECONDAIRES PREJUDICIABLES AU CIRCUIT INTEGRE. INPUT PROTECTION AGAINST ACCIDENTAL OVERVOLTAGES FOR MOS TYPE INTEGRATED CIRCUIT DEVICES WITH LOW SUPPLY VOLTAGE AND HIGH INTEGRATION DENSITY, INCLUDING IGFETs (ISOLATED TRIGGER TRANSISTORS) WITH TRIGGER WAVE OXIDES A THICKNESS THAT DOES NOT EXCEED 500A. IT IS ESSENTIALLY CONSTITUTED BY A LATERAL BIPOLAR TRANSISTOR T WHOSE TRANSMITTER IS CONNECTED TO EARTH AND THE COLLECTOR IS CONNECTED TO INPUT I AND TO THE GACHETTE ELECTRODES OF IGFET M. THE BASE REGION IS STRONGLY DOPED BY IONIC IMPLANTATION D 'IMPURITIES WHOSE CONCENTRATION IS GREATER THAN THAT OF THE OTHER REGIONS OF THE INTEGRATED CIRCUIT HAVING THE SAME POLARITY. IN THIS WAY, THE BREAKDOWN VOLTAGE AT THE PROTECTION LEVEL IS LESS THAN THE BREAKDOWN VOLTAGE AT THE REMAINING CIRCUIT LEVEL: THE THIN TRIGGER OXIDES ARE PROTECTED AGAINST BREAKAGE WITHOUT HARMFUL SIDE EFFECTS TO THE INTEGRATED CIRCUIT.

Inventors

• 👤 Livio Baldi

Bibliographic Details