EP1798762A2
Active / In Force
EP
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Semiconductor devices including implanted regions and protective layers and methods of forming the same
Assignee: Wolfspeed Inc
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Filing: 2006-12-13
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Granted: —
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Expires: 2026-12-13
Abstract
Abstract Methods of forming a semiconductor device include forming a protective layer (24) on a semiconductor layer, implanting ions having a first conductivity type through the protective layer (24) into the semiconductor layer to form an implanted region (31) of the semiconductor layer, and annealing the semiconductor layer and the protective layer (24) to activate the implanted ions. An opening is formed in the protective layer (24) to expose the implanted region (31) of the semiconductor layer, and an electrode is formed in the opening. A semiconductor structure includes a Group III-nitride semiconductor layer, a protective layer (24) on the semiconductor layer, a distribution of implanted dopants within the semiconductor layer, and an ohmic contact (30) extending through the protective layer to the semiconductor layer.
Inventors
- 👤 Scott T Sheppard
- 👤 Adam William Saxler
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-25 15:13
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/40; H10D30/47; H10D30/471; H10D30/475; H10D30/4755; H10D12/00; H10D12/01; H10D12/031; H10D30/01; H10D30/015; H10D62/00; H10D62/80; H10D62/83; H10D62/832; H10D62/8325; H10P; H10P30/00; H10P30/20; H10P30/202; H10P30/204; H10P30/2042; H10P30/206; H10P30/21; H10P30/212; H10P30/218; H10D62/85; H10D62/8503
Claims Analysis
Total Claims: 42
Claim 1
Independent Claim
83 words
A method of forming a semiconductor device, comprising: forming a protective layer (24) on a semiconductor layer; implanting ions having a first conductivity type through the protective layer (24) into the semiconductor layer to form an implanted region (31) of the semiconductor layer; annealing the semiconductor layer and the protective layer (24) to activate the implanted ions; forming an opening in the protective layer (24) to expose the implanted region (31) of the semiconductor layer; and forming an electrode (30) in the opening.
Claim 2
Dependent Claim
14 words
The method of claim 1, wherein the semiconductor layer comprises a Group III-nitride material.
Claim 3
Dependent Claim
15 words
The method of claim 1 or 2, wherein the semiconductor layer comprises an epitaxial layer.
Claim 4
Dependent Claim
30 words
The method of claim 3, wherein the epitaxial layer is formed in a reaction chamber, and the protective layer is formed in the same reaction chamber as the semiconductor layer.
Claim 5
Dependent Claim
16 words
The method of claim 1, wherein the protective layer (24) comprises SiN, SiO 2 and/or SiON.
Claim 6
Dependent Claim
22 words
The method of claim 5, wherein the protective layer (24) is formed by MOCVD and/or LPCVD at a temperature greater than 700°C.
Claim 7
Dependent Claim
13 words
The method of claim 5, wherein the protective layer (24) comprises stoichiometric SiN.
Claim 8
Independent Claim
21 words
The method of any preceding claim, wherein annealing the semiconductor layer and the protective layer comprises annealing in an inert gas.
Claim 9
Dependent Claim
29 words
The method of claim 1, wherein the protective layer comprises SiN and annealing the semiconductor layer and the protective layer comprises annealing in an atmosphere containing NH 3 .
Claim 10
Independent Claim
15 words
The method of any preceding claim, wherein the implanted ions comprise Si, S or 0.
Claim 11
Independent Claim
15 words
The method of any preceding claim, wherein the electrode comprises a source and/or drain contact.
Claim 12
Independent Claim
25 words
The method of any preceding claim, wherein annealing the semiconductor layer and the protective layer comprises annealing at a temperature of about 1000°C or greater.
Claim 13
Dependent Claim
26 words
The method of claim 12, wherein annealing the semiconductor layer and the protective layer comprises annealing at a temperature of from about 1000°C to about 1300°C.
Claim 14
Dependent Claim
36 words
The method of claim 12, wherein annealing the semiconductor layer and the protective layer comprises annealing at a temperature sufficient to activate the implanted ions but less than a temperature at which the semiconductor layer deteriorates.
Claim 15
Dependent Claim
30 words
The method of claim 1, wherein annealing the semiconductor layer and the protective layer comprises annealing in NH 3 and SiH 4 so that SiN is formed during the anneal.
Claim 16
Independent Claim
29 words
The method of any preceding claim, wherein the implantation energy is selected to provide a peak implant concentration near an interface of the semiconductor layer and the protective layer.
Claim 17
Dependent Claim
17 words
The method of claim 16, wherein the implant dose is about 4x10 14 ions/cm 2 or greater.
Claim 18
Dependent Claim
18 words
The method of claim 17, wherein the implant dose is greater than about 2x10 15 ions/cm 2 .
Claim 19
Dependent Claim
21 words
The method of claim 17, wherein the peak implant concentration is greater than about 1 x 10 20 cm -3 .
Claim 20
Dependent Claim
19 words
The method of claim 17, wherein the peak implant concentration is greater than about 3x10 20 cm 3 .
Claim 21
Dependent Claim
70 words
The method of claim 1, wherein forming an opening in the protective layer (24) comprises forming a first opening in the protective layer and forming an electrode (30) in the opening comprises forming a source/drain electrode in the first opening, the method further comprising: forming a second opening in the protective layer to expose a non-implanted region of the semiconductor layer; and forming a gate electrode in the second opening.
Claim 22
Dependent Claim
22 words
The method of claim 21, wherein forming the gate electrode and forming the source/drain electrode are performed in a same metallization process.
Claim 23
Independent Claim
12 words
The method of any preceding claim, wherein the semiconductor layer comprises SiC.
Claim 24
Dependent Claim
41 words
A semiconductor structure comprising: a Group III-nitride semiconductor layer; a protective layer (24) on the semiconductor layer; a distribution of implanted dopants within the semiconductor layer; and an ohmic contact (30) extending through the protective layer (24) to the semiconductor layer.
Claim 25
Dependent Claim
18 words
The semiconductor structure of claim 24, wherein the protective layer (24) comprises SiN, SiO 2 , and/or SiON.
Claim 26
Dependent Claim
14 words
The semiconductor structure of claim 25, wherein the protective layer (24) comprises stoichiometric SiN.
Claim 27
Dependent Claim
19 words
The semiconductor structure of any claim 24 to 26, wherein the implanted dopants comprise Si, S and/or O atoms.
Claim 28
Dependent Claim
30 words
The semiconductor structure of any claim 24 to 27, wherein the distribution of implanted dopants has a peak concentration near an interface of the semiconductor layer and the protective layer.
Claim 29
Dependent Claim
30 words
The semiconductor structure of any claim 24 to 27, wherein the distribution of implanted dopants has a peak concentration beneath an interface of the semiconductor layer and the protective layer.
Claim 30
Dependent Claim
28 words
The semiconductor structure of any claim 24 to 27, wherein the distribution of implanted dopants extends through the semiconductor layer and into a layer beneath the semiconductor layer.
Claim 31
Dependent Claim
21 words
The semiconductor structure of any claim 24 to 30, wherein the ohmic contact is in direct contact with the protective layer.
Claim 32
Dependent Claim
37 words
The semiconductor structure of any claim 24 to 31, further comprising: a non-ohmic metal contact extending through the protective layer to the semiconductor layer, wherein the non-ohmic metal contact comprises the same material as the ohmic contact.
Claim 33
Dependent Claim
62 words
A transistor device comprising: a Group III-nitride semiconductor layer including source and drain regions; a SiN protective layer (24) on the semiconductor layer; a distribution of implanted dopants within the source and drain regions of the semiconductor layer; and source and drain ohmic contacts (30) extending through the protective layer (24) to the source and drain regions, respectively, of the semiconductor layer.
Claim 34
Dependent Claim
14 words
The transistor device of claim 33, wherein the protective layer (24) comprises stoichiometric SiN.
Claim 35
Dependent Claim
18 words
The transistor device of claim 33 or 34, wherein the implanted dopants comprise Si, S and/or O atoms.
Claim 36
Dependent Claim
30 words
The transistor device of claim 33, 34 or 35, wherein the distribution of implanted dopants has a peak concentration near an interface of the semiconductor layer and the protective layer.
Claim 37
Dependent Claim
30 words
The transistor device of claim 33, 34 or 35, wherein the distribution of implanted dopants has a peak concentration beneath an interface of the semiconductor layer and the protective layer.
Claim 38
Dependent Claim
28 words
The transistor device of claim 33, 34 or 35, wherein the distribution of implanted dopants extends through the semiconductor layer and into a layer beneath the semiconductor layer.
Claim 39
Dependent Claim
21 words
The transistor device of any claim 33 to 38, wherein the ohmic contact is in direct contact with the protective layer
Claim 40
Dependent Claim
40 words
The transistor device of any claim 33 to 39, further comprising: a non-ohmic metal contact extending through the SiN protective layer to the Group III-nitride semiconductor layer, wherein the non-ohmic metal contact comprises the same material as the ohmic contact.
Claim 41
Dependent Claim
28 words
The transistor device of any claim 33 to 40, wherein the distribution of implanted dopants has a peak implant concentration greater than about 1x10 20 cm -3 .
Claim 42
Dependent Claim
28 words
The transistor device of any claim 33 to 40, wherein the distribution of implanted dopants has a peak implant concentration greater than about 3x10 20 cm -3 .
References Cited (Backward Citations)
No citation records indexed.
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