EP1357433A2
Expired / Lapsed
EP
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Method of fabricating sub-lithographic sized line and space patterns
Assignee: HP Inc
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Filing: 2003-04-17
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Granted: —
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Expires: 2023-04-17
Abstract
Abstract A method for fabricating sub-lithographic sized line and space features is disclosed. The method includes the use of conventional microelectronics processing techniques such as photolithographic patterning and etching, polysilicon deposition, polysilicon oxidation, polysilicon oxide etching, polysilicon wet and plasma etching, and chemical mechanical planarization. Polysilicon line features 21 having a feature size that is greater than or equal to a lithography limit λ are oxidized in a plasma that includes an oxygen gas. The oxidation forms a sub-lithographic sized polysilicon core and an oxidized polysilicon mantel 22 that includes portions along sidewall surfaces of the sub-lithographic sized polysilicon core that also have a sub-lithographic feature size. After planarization and a plasma etch that is selective to either the polysilicon or the oxidized polysilicon, a plurality of sub-lithographic sized line 21 and space 20 patterns are formed. Those line and space patterns (21, 20) can be used for an imprinting stamp for nano-imprint lithography.
Inventors
- 👤 Heon Lee
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 23:42
CPC Classifications
G; G03; G03F; G03F7/00; G03F7/0002; B; B82; B82Y; B82Y10/00; B82Y40/00; G03F7/0017; H; H10; H10P; H10P76/00; H10P76/40; H10P76/408; H10P76/4088; H10P50/00; H10P50/71; H10P50/73
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
285 words
A method of fabricating sub-lithographic sized line and space patterns, comprising: depositing a first polysilicon layer 17 on a surface 6 of a base layer 13 ; depositing a photoresist layer 15 on a surface 12 of the first polysilicon layer 17 ; patterning and then etching the photoresist layer 15 to define a line and space
pattern ( 23, 24 ) therein; transferring the line and space pattern ( 23, 24 ) to the first polysilicon layer 17 by
etching the first polysilicon layer 17 to define a plurality of polysilicon line features 21 and
space features 20 , the polysilicon line features 21 and the space features 20 including a
minimum feature size that is greater than or equal to a lithography limit λ of a lithographic
system used for the patterning; removing the photoresist layer 23 from the polysilicon line features 21 ; oxidizing the polysilicon line features 21 in a plasma comprising an oxygen gas,
and continuing the oxidizing until the polysilicon line features 21 are reduced to a sub-lithographic
feature size and an oxidized mantel 22 of the polysilicon line features 21 has
expanded e thereby reducing the space features 20 to the sub-lithographic feature size; depositing a second polysilicon layer 25 that completely covers the oxidized mantel 22 of the polysilicon line features 21 and completely fills in the space features 20 ; planarizing the second polysilicon layer 25 to form a planar layer of alternating and
sub-lithographic sized polysilicon ( 21, 25 ) and oxidized polysilicon line features 22 ; and etching the planar layer to selectively remove a selected one of the
polysilicon line features ( 21, 25 ) or the oxidized polysilicon line features 22 .
Claim 2
Dependent Claim
25 words
A method as claimed in Claim 1, wherein the planar layer is etched by
means of a wet etch process or a plasma etching process.
Claim 3
Dependent Claim
42 words
A method as claimed in Claim 1 or 2, wherein the photoresist layer 23 is
removed by means of a wet etch process, a wet cleaning process using an organic
solvent, or an ashing process in a plasma comprising an oxygen gas.
Claim 4
Independent Claim
106 words
A method as claimed in any preceding Claim, wherein both the removing
the photoresist step and the oxidizing the polysilicon line features step occur as
part of a simultaneous process comprising: ashing the photoresist layer 23 in a plasma comprising an oxygen gas to
remove the photoresist layer 23 while simultaneously oxidizing the polysilicon line
features 21 in the plasma comprising the oxygen gas, and continuing the oxidizing
until the polysilicon line features 21 are reduced to a sub-lithographic feature size
and an oxidized mantel 22 of the polysilicon line features 21 has expanded e thereby reducing the space features 20 to the sub-lithographic feature size.
Claim 5
Independent Claim
17 words
A method as claimed in any preceding Claim, wherein the base layer 13 comprises a dielectric material.
Claim 6
Independent Claim
20 words
A method as claimed in any preceding Claim, wherein the base layer 13 is
connected with a substrate 11 .
Claim 7
Dependent Claim
19 words
A method as claimed in Claim 6, wherein the substrate 11 is a
semiconductor substrate or a silicon substrate.
Claim 8
Independent Claim
22 words
A method as claimed in any preceding Claim, wherein the lithography limit λ
is greater than or equal to about 100.0 nanometers.
Claim 9
Independent Claim
16 words
A method as claimed in any preceding claim, wherein the planarization step
comprises chemical mechanical polishing.
Claim 10
Independent Claim
171 words
A method as claimed in any preceding claim, wherein the etching the planar
layer step comprises selectively removing the oxidized polysilicon features, and
further comprising: oxidizing the polysilicon line features 21 in a plasma comprising an oxygen
gas, and continuing the oxidizing until the sub-lithographic feature size of the
polysilicon line features 21 are further reduced and an oxidized mantel 22 of the
polysilicon line features 21 has expanded e thereby further reducing the sub-lithographic
feature size of the space features 20 ; depositing a third polysilicon layer 29 that completely covers the oxidized
mantel 22 of the polysilicon line features 21 and completely fills in the space
features 20 ; planarizing the third polysilicon layer 29 to form a planar layer of alternating
and sub-lithographic sized polysilicon line features ( 21, 25, 29 ) and oxidized
polysilicon line features 27 ; and etching the planar layer to selectively remove a selected one of the
polysilicon line features ( 21, 25, 29 ) or the oxidized polysilicon line features 27 .
References Cited (Backward Citations)
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