EP1146644A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Method and circuit for correcting a duty-cycle of a signal
Assignee: Samsung Electronics Co Ltd
•
Filing: 2001-04-10
•
Granted: —
•
Expires: 2021-04-10
Abstract
Abstract A signal is duty-cycle corrected by delaying the signal to generate a delayed version of the signal and generating an output signal that transitions from a first state to a second state responsive to a transition of the signal from the first state to the second state and a transition of the delayed version of the signal from the second state to the first state. The output signal transitions from the second state to the first state responsive to a transition of the signal from the second state to the first state and a transition of the delayed version of the signal from the first state to the second state.
Inventors
- 👤 Kyu-Hyoun Kim
- 👤 Jung-Bae Lee
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-27 21:40
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/01; H03K5/04; H03K5/156; H03K5/1565; H03K5/13; H03K5/133; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/081; H03L7/0812; H03L7/0816; H03L2207/00; H03L2207/12; Y; Y10; Y10S; Y10S331/00; Y10S331/02
Claims Analysis
Total Claims: 32
Claim 1
Independent Claim
113 words
A method of correcting a duty-cycle of a signal, comprising: delaying the signal to generate a delayed version of the signal; and generating an output signal that transitions from a first state to a second state
responsive to a transition of the signal from the first state to the second state and a
transition of the delayed version of the signal from the second state to the first state,
and that transitions from the second state to the first state responsive to a transition of
the signal from the second state to the first state and a transition of the delayed version
of the signal from the first state to the second state.
Claim 2
Dependent Claim
61 words
The method of Claim 1, wherein generating the output signal
comprises: inverting the delayed version of the signal to generate an inverted delayed
version of the signal; limiting a slew rate of the signal to generate a first intermediate output signal;
and limiting a slew rate of the inverted delayed version of the signal to generate a
second intermediate output signal.
Claim 3
Dependent Claim
42 words
The method of Claim 2, wherein generating the output signal further
comprises: determining a voltage difference between the first and second intermediate
output signals; and generating the output signal responsive to the voltage difference between the
first and second intermediate output signals.
Claim 4
Dependent Claim
68 words
The method of Claim 1, wherein delaying the signal to generate the
delayed version of the signal comprises: determining a phase difference between the signal and the delayed version of
the signal; generating a control voltage responsive to the phase difference between the
signal and the delayed version of the signal; and delaying the signal to generate the delayed version of the signal responsive to
the control voltage.
Claim 5
Dependent Claim
95 words
The method of Claim 1, wherein the output signal transitions from the
first state to the second state between the transition of the signal from the first state to
the second state and the transition of the delayed version of the signal from the second
state to the first state, and the output signal transitions from the second state to the
first state between the transition of the signal from the second state to the first state
and the transition of the delayed version of the signal from the first state to the second
state.
Claim 6
Dependent Claim
81 words
The method of Claim 1, wherein delaying the signal to generate a
delayed version of the signal comprises: delaying the signal for a predetermined time to generate the delayed version of
the signal, wherein the predetermined time is selected from the group consisting of a
time in which the signal is in the first state during a single cycle of the signal and a
time in which the signal is in the second state during the single cycle of the signal.
Claim 7
Independent Claim
87 words
A method of correcting a duty-cycle of a signal, comprising: limiting a slew rate of the signal to generate a first intermediate output signal; determining a voltage difference between the first intermediate output signal
and a reference voltage; generating an output signal responsive to the voltage difference between first
intermediate output signal and the reference voltage; delaying the output signal to generate a delayed version of the output signal;
and generating the reference voltage responsive to the output signal and a delayed
version of the output signal.
Claim 8
Dependent Claim
76 words
The method of Claim 7, wherein delaying the output signal to generate
the delayed version of the output signal comprises: determining a phase difference between the output signal and the delayed
version of the output signal; generating a control voltage responsive to the phase difference between the
output signal and the delayed version of the output signal; and delaying the output signal to generate the delayed version of the output signal
responsive to the control voltage.
Claim 9
Dependent Claim
49 words
The method of Claim 7, wherein generating the reference voltage
comprises: determining a phase difference between the output signal and the delayed
version of the output signal; and generating the reference voltage responsive to the phase difference between
the output signal and the delayed version of the output signal.
Claim 10
Dependent Claim
116 words
A duty-cycle correction circuit, comprising: a delay circuit that is configured to generate a delayed signal responsive to an
input signal; and a mixer circuit that is configured to generate an output signal that transitions
from a first state to a second state responsive to a transition of the input signal from
the first state to the second state and a transition of the delayed signal from the second
state to the first state, and that transitions from the second state to the first state
responsive to a transition of the input signal from the second state to the first state and
a transition of the delayed signal from the first state to the second state.
Claim 11
Dependent Claim
31 words
The duty-cycle correction circuit of Claim 10, further comprising: a first inverter that is configured to generate an inverted delayed signal at an
output terminal thereof responsive to the delayed signal.
Claim 12
Dependent Claim
86 words
The duty-cycle correction circuit of Claim 11, wherein the mixer
circuit comprises: a second inverter that is configured to generate a first intermediate output
signal at an output terminal thereof responsive to the input signal; a third inverter that is configured to generate a second intermediate output
signal at an output terminal thereof responsive to the inverted delayed signal; and a fourth inverter that is configured to generate the output signal responsive to
the first and second intermediate output signals received at an input terminal thereof.
Claim 13
Dependent Claim
51 words
The duty-cycle correction circuit of Claim 11, further comprising: a first slew-rate limiter circuit that is configured to generate a first intermediate
output signal responsive to the input signal; and a second slew-rate limiter circuit that is configured to generate a second
intermediate output signal responsive to the inverted delayed signal.
Claim 14
Dependent Claim
30 words
The duty-cycle correction circuit of Claim 13, further comprising: a differential amplifier circuit that is configured to generate the output signal
responsive to the first and second intermediate output signals.
Claim 15
Dependent Claim
76 words
The duty-cycle correction circuit of Claim 10, wherein the delay circuit
comprises: a phase detector circuit that is configured to determine a phase difference
between the input signal and the delayed signal; a control voltage generator circuit that is configured to generate a control
voltage responsive to the phase difference between the input signal and the delayed
signal; and a delay line circuit that is configured to generate the delayed signal responsive
to the control voltage.
Claim 16
Dependent Claim
18 words
The duty-cycle correction circuit of Claim 10, wherein the control
voltage generator circuit comprises a charge pump circuit.
Claim 17
Dependent Claim
64 words
A duty-cycle correction circuit, comprising: a differential amplifier circuit that is configured to generate an output signal
responsive to the an input signal and a reference voltage; a delay circuit that is configured to generate a delayed signal responsive to the
output signal; and a control circuit that is configured to generate the reference voltage responsive
to the output signal and the delayed signal.
Claim 18
Dependent Claim
52 words
The duty-cycle correction circuit of Claim 17, further comprising: a slew-rate limiter circuit that is configured to generate a first intermediate
output signal responsive to an input signal; and wherein the differential amplifier circuit is configured to generate the output
signal responsive to the first intermediate output signal and the reference voltage.
Claim 19
Dependent Claim
76 words
The duty-cycle correction circuit of Claim 17, wherein the delay circuit
comprises: a phase detector circuit that is configured to determine a phase difference
between the input signal and the delayed signal; a control voltage generator circuit that is configured to generate a control
voltage responsive to the phase difference between the input signal and the delayed
signal; and a delay line circuit that is configured to generate the delayed signal responsive
to the control voltage.
Claim 20
Dependent Claim
18 words
The duty-cycle correction circuit of Claim 19, wherein the control
voltage generator circuit comprises a charge pump circuit.
Claim 21
Dependent Claim
64 words
The duty-cycle correction circuit of Claim 17, wherein the control
circuit comprises: a phase detector that is configured to determine a phase difference between the
output signal and the delayed version of the input signal; and an integrator circuit that is configured to generate the reference voltage
responsive to the phase difference between the output signal and the delayed version
of the input signal.
Claim 22
Dependent Claim
16 words
The duty-cycle correction circuit of Claim 21, wherein the integrator
circuit comprises a charge pump circuit.
Claim 23
Dependent Claim
16 words
The duty-cycle correction circuit of Claim 22, wherein the integrator
circuit comprises a low-pass filter circuit.
Claim 24
Dependent Claim
112 words
A duty-cycle correction circuit, comprising: means for delaying a signal to generate a delayed version of the signal; and means for generating an output signal that transitions from a first state to a
second state responsive to a transition of the signal from the first state to the second
state and a transition of the delayed version of the signal from the second state to the
first state, and that transitions from the second state to the first state responsive to a
transition of the signal from the second state to the first state and a transition of the
delayed version of the signal from the first state to the second state.
Claim 25
Dependent Claim
72 words
The duty-cycle correction circuit of Claim 24, wherein the means for
generating the output signal comprises: means for inverting the delayed version of the signal to generate an inverted
delayed version of the signal; means for limiting a slew rate of the signal to generate a first intermediate
output signal; and means for limiting a slew rate of the inverted delayed version of the signal to
generate a second intermediate output signal.
Claim 26
Dependent Claim
51 words
The duty-cycle correction circuit of Claim 25, wherein the means for
generating the output signal further comprises: means for determining a voltage difference between the first and second
intermediate output signals; and means for generating the output signal responsive to the voltage difference
between the first and second intermediate output signals.
Claim 27
Dependent Claim
79 words
The duty-cycle correction circuit of Claim 24, wherein the means for
delaying the signal to generate the delayed version of the signal comprises: means for determining a phase difference between the signal and the delayed
version of the signal; means for generating a control voltage responsive to the phase difference
between the signal and the delayed version of the signal; and means for delaying the signal to generate the delayed version of the signal
responsive to the control voltage.
Claim 28
Dependent Claim
97 words
The duty-cycle correction circuit of Claim 24, wherein the output
signal transitions from the first state to the second state between the transition of the
signal from the first state to the second state and the transition of the delayed version
of the signal from the second state to the first state, and the output signal transitions
from the second state to the first state between the transition of the signal from the
second state to the first state and the transition of the delayed version of the signal
from the first state to the second state.
Claim 29
Dependent Claim
88 words
The duty-cycle correction circuit of Claim 24, wherein the means for
delaying the signal to generate a delayed version of the signal comprises: means for delaying the signal for a predetermined time to generate the delayed
version of the signal, wherein the predetermined time is selected from the group
consisting of a time in which the signal is in the first state during a single cycle of the
signal and a time in which the signal is in the second state during the single cycle of
the signal.
Claim 30
Dependent Claim
92 words
A duty-cycle correction circuit, comprising: means for limiting a slew rate of a signal to generate a first intermediate output
signal; means for determining a voltage difference between the first intermediate
output signal and a reference voltage; means for generating an output signal responsive to the voltage difference
between first intermediate output signal and the reference voltage; means for delaying the output signal to generate a delayed version of the
output signal; and means for generating the reference voltage responsive to the output signal and
a delayed version of the output signal.
Claim 31
Dependent Claim
87 words
The duty-cycle correction circuit of Claim 30, wherein the means for
delaying the output signal to generate the delayed version of the output signal
comprises: means for determining a phase difference between the output signal and the
delayed version of the output signal; means for generating a control voltage responsive to the phase difference
between the output signal and the delayed version of the output signal; and means for delaying the output signal to generate the delayed version of the
output signal responsive to the control voltage.
Claim 32
Dependent Claim
58 words
The duty-cycle correction circuit of Claim 30, wherein the means for
generating the reference voltage comprises: means for determining a phase difference between the output signal and the
delayed version of the output signal; and means for generating the reference voltage responsive to the phase difference
between the output signal and the delayed version of the output signal.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.