EP1137226A2
Expired / Lapsed
EP
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Improved packet scheduling of real time information over a packet network
Assignee: Texas Instruments Inc
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Filing: 2001-03-09
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Granted: —
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Expires: 2021-03-09
Abstract
Abstract One method of processing first and second received packets of real-time information includes computing for each of said received packets respective deadline intervals and ordering processing of the first and second received packets according to the respective deadline intervals. A single-chip integrated circuit has a processor circuit and embedded electronic instructions forming an egress packet control establishing an egress scheduling list structure and operations in the processor circuit that extract a packet deadline intervals DI, place packets in the egress scheduling list according to deadline intervals DI; and embed a decoder that decodes the packets according to a priority depending to their deadline intervals. Embedded electronic instructions establish an egress scheduling list structure and operations in the processor circuit that establish channel decoders on non-coincident frame boundaries and a packet engine to detect when a first packet has a first deadline and is currently in decode while a second packet is just-arriving and has a second deadline earlier than the first deadline. The packet engine establishes a determination whether both the second and first packets can be decoded ahead of their respective deadlines if the second packet were decoded preemptively, and if so, then preempts the processor circuit channel decoder structure to decode the second packet. Other processes, integrated circuits, chipsets, wireless telephones, PBXs, line cards, computers, routers, and networks for voice over packet, media over packet and real-time transmissions over packet are disclosed.
Inventors
- 👤 Andrew M. Welin
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-05 06:12
CPC Classifications
H; H04; H04L; H04L47/00; H04L47/10; G; G10; G10L; G10L25/00; G10L25/78; H04L12/00; H04L12/64; H04L12/6418; H04L47/24; H04L47/2416; H04L47/245; H04L47/28; H04L47/283; H04L47/32; H04L47/34; H04L47/50; H04L47/56; H04L47/562; H04L47/564; H04L47/62; H04L47/622; H04L47/6235; H04L65/00; H04L65/1066; H04L65/1101; H04L65/1106; H04L65/80; H04M; H04M1/00; H04M1/253; H04M1/2535; H04L2012/6464; H04L2012/6481; H04L2012/6489; H04L2012/6494
Claims Analysis
Total Claims: 28
Claim 1
Independent Claim
60 words
An electronic system comprising: a processor circuit; an egress packet control having stored instructions that
generate for first and second received packets respective
deadline intervals and order the processing in the processor
circuit of the first and second received packets according to
the respective deadline intervals; and a printed wiring assembly bearing the processor circuit and
the egress packet control.
Claim 2
Dependent Claim
64 words
An electronic system as claimed in claim 1 further comprising telephone interface circuitry having plural connectors ready
for connection to plural telephone units; a digital network interface; and an integrated circuit assembly coupling the telephone
interface circuitry to the digital network interface, the
integrated circuit assembly including said printed wiring
assembly and providing voice over packet transmission and
reception as a private branch exchange.
Claim 3
Dependent Claim
60 words
An electronic system as claimed in claim 1 further
comprising cellular telephone wireless transmit/receive interface
circuitry, a packet network interface; and an integrated circuit assembly coupling the cellular telephone
wireless transmit/receive interface circuitry to the packet
network interface, the integrated circuit assembly including
said printing wiring assembly and providing voice over packet
transmission and reception as a wireless base station.
Claim 4
Dependent Claim
27 words
An electronic system as claimed in claim 1 further
comprising a single-chip integrated circuit including the
processor circuit and the stored instructions of the egress
packet control.
Claim 5
Dependent Claim
30 words
An electronic system as claimed in claim 1 wherein the
stored instructions define temporary storing of information
about the packets on a queue in order of the respective deadline
intervals.
Claim 6
Dependent Claim
23 words
An electronic system as claimed in claim 5 wherein the stored
instructions further define periodic decrementing of the
deadline intervals as time passes.
Claim 7
Dependent Claim
56 words
An electronic system as claimed in claim 5 wherein the stored
instructions further define computing for a third received
packet a further deadline interval and sorting the queue to
insert information about the third received packet on the
queue in order of its further deadline interval relative to
the respective deadline intervals already on the queue.
Claim 8
Dependent Claim
29 words
An electronic system as claimed in claim 5 wherein the stored
instructions further define decoding a packet having the
shortest time to deadline as expressed by its deadline
interval.
Claim 9
Dependent Claim
70 words
An electronic system as claimed in claim 1 wherein the stored
instructions further define generation of information about
the packets in the form of primary keys comprising deadline
intervals and secondary keys comprising frame sizes, and
temporarily storing information about the packets on a queue
in order of the primary keys, and for packets having identical
primary keys storing the information about the packets in
order of the secondary keys.
Claim 10
Dependent Claim
39 words
An electronic system as claimed in claim 1 wherein the
egress packet control defines for an arriving packet the
deadline interval DI as the difference between an arrival time
A of the arriving packet and a deadline time D.
Claim 11
Dependent Claim
62 words
An electronic system as claimed in claim 1wherein the
egress packet control defines the deadline interval Dj for an
arriving packet j, having a sequence number Sj and frame width
F, from a deadline Di of an earlier packet i having a sequence
number Si, substantially as a function of frame width F and
the difference of sequence numbers Sj and Si.
Claim 12
Dependent Claim
79 words
An electronic system as claimed in claim 1 wherein an
arriving silence packet j represents a number of silence
frames S having a frame width F, and the egress packet control
defines a deadline interval DIj for the arriving silence
packet j from a deadline interval DIi previously determined
for an earlier packet i, substantially as the sum of the
deadline interval DIi added to a product of the number of
silence frames S times the frame width F.
Claim 13
Dependent Claim
50 words
An electronic system as claimed in claim 1 wherein the
egress packet control has stored instructions that: define buffers; compute sizes of respective information reserves in
the buffers; and order processing of the packets according to a
priority depending at least in part on the sizes of the
respective reserves.
Claim 14
Dependent Claim
56 words
An electronic system as claimed in claim 1 wherein the
egress packet control has stored instructions to preempt
processing of the first received packet, by preemptively
processing the second received packet, when the deadline
interval for the second received packet is less than the
deadline interval respective to the first received packet by a
predetermined amount.
Claim 15
Dependent Claim
49 words
An electronic system as claimed in claim 1 wherein the
egress packet control has stored instructions for ingress
packet processing, and for preempting egress packet processing
of an egress packet having a deadline interval exceeding a
value, by preemptively executing ingress packet processing of
at least one ingress packet.
Claim 16
Dependent Claim
69 words
An electronic system as claimed in claim 1 having channel
decoders that operate on non-coincident frame boundaries, and
wherein if the second packet has a second deadline earlier
than the first deadline, the egress packet control has stored
instructions for testing to determine whether both the second
and first packets can be decoded ahead of their respective
deadlines, and if so, then preemptively executing decode of
the second packet.
Claim 17
Dependent Claim
85 words
An electronic system as claimed in claim 1 wherein the
egress packet control has stored instructions for a process of
generating data descriptive of circular time differences
between times of events A and B, the process comprising: electronically subtracting a value representative of the
time of event B from a value representative of the time of
event A, there resulting a most significant bit (MSB); and providing the MSB itself as a flag indicating which of
events A and B is prior to the other.
Claim 18
Dependent Claim
87 words
An electronic system as claimed in claim 17 wherein the
stored instructions are further for: electronically subtracting and delivering to a storage element
a value representative of the time of event B from a value
representative of the time of event A, resulting in an
electronic representation (delta) having the most significant
bit (MSB) and a sign bit S; and electronically processing the electronic representation
(delta) and a predetermined value (TMAX) in response to the MSB
and the sign bit S to generate the circular time difference.
Claim 19
Dependent Claim
44 words
An electronic system as claimed in claim 1 whereas the
egress packet control has stored instructions for the
computing for each of said received packets respective
deadline intervals as circular time differences between a
respective deadline D and a respective packet arrival time A.
Claim 20
Dependent Claim
82 words
A wireless telephone comprising an antenna, a voice
transducer, and at least one integrated circuit assembly
coupling the voice transducer to the antenna, said at least one
integrated circuit assembly providing voice over packet
transmissions and having embedded electronic instructions
comprising an ingress/egress packet control to process egress
information and determine lowest first egress deadline interval
DI and further execute an ingress process preempting the egress
process when the value of lowest first egress deadline interval
DI exceeds a predetermined amount K.
Claim 21
Dependent Claim
95 words
A wireless telephone comprising an antenna, a voice
transducer, and at least one integrated circuit assembly
coupling the voice transducer to the antenna, said at least one
integrated circuit assembly adapted to generate data descriptive
of circular time differences between times of events A and B by
electronically subtracting a value representative of the time of
event B from a value representative of the time of event A,
there resulting a most significant bit (MSB); and providing the
MSB itself as a flag indicating which of events A and B is prior
to the other.
Claim 22
Dependent Claim
100 words
A wireless telephone as claimed in claim 21 wherein the
integrated circuit assembly is adapted to generate circular time
differences between times of events A and B by electronically
subtracting and delivering to a storage element a value
representative of the time of event B from a value
representative of the time of event A, resulting in an
electronic representation (delta) having a most significant bit
(MSB) and a sign bit S; and electronically process the
electronic representation (delta) and a predetermined value
(TMAX) in response to the MSB and the sign bit S to generate the
circular time difference.
Claim 23
Dependent Claim
73 words
A single-chip integrated circuit comprising: storage for values representative of the time of two events; an adder/subtractor coupled to the storage and operative to
generate a difference value (delta) and deliver the difference
value into said storage thereby resulting a most significant
bit (MSB) of the difference value (delta); and a flag register having a bit fed with said MSB to
indicating which of events A and B is prior to the other.
Claim 24
Dependent Claim
49 words
A single-chip integrated circuit as claimed in claim 23
further having: logic circuitry responsive to the MSB and a sign bit S of the
electronic difference (delta) and a predetermined value (TMAX),
the logic circuitry for driving said adder/subtractor to
generate the circular time difference of the two events.
Claim 25
Independent Claim
42 words
A method of processing first and second received packets of
real-time information, comprising the steps of: computing for each of said received packets respective
deadline intervals; and ordering processing of the first and second received
packets according to the respective deadline intervals.
Claim 26
Dependent Claim
68 words
A process of generating data descriptive of circular time
differences between times of events A and B, the process
comprising: electronically subtracting a value representative of the
time of event B from a value representative of the time of event
A, there resulting a most significant bit (MSB); and providing the MSB itself as a flag indicating which of
events A and B is prior to the other.
Claim 27
Dependent Claim
85 words
A process of generating circular time differences as
claimed in claim 26 further comprising: electronically delivering to a storage element a value
representative of the time of event B subtracted from a value
representative of the time of event A, resulting in an
electronic representation (delta) having the most significant
bit (MSB) and a sign bit S; and electronically processing the electronic representation
(delta) and a predetermined value (TMAX) in response to the
MSB and the sign bit S to generate the circular time
difference.
Claim 28
Dependent Claim
49 words
A single chip integrated circuit comprising: a processor circuit; and an egress packet control having stored instructions that
generate for first and second received packets respective
deadline intervals and order the processing in the processor
circuit of the first and second received packets according to
the respective deadline intervals.
References Cited (Backward Citations)
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