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EP1115094A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Data processing device and its method of operation

Assignee: NXP BV
•
Filing: 2000-12-22
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Granted: —
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Expires: 2020-12-22
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Abstract

Abstract During a cryptographic operation in the integrated circuit at least two processors, CPU or co-processors are used in parallel at same time. Single current paths can no longer be reconstructed as current paths of the two parallel operating processors add together, so differential power analysis cannot be used. Smart card or chip card contains data processing circuitry with CPU or co-processor (10), co-processor (12), with divider (18) between processors and data input (14). Divider divides cryptographic operation into first and second part operations (20,22) with random input (24) to feed data parts to the processors. During the cryptographic operation the two processors operate in parallel at same time. Single current paths can no longer be reconstructed as current paths of the two parallel operating processors add together, so differential power analysis cannot be used.

Inventors

  • 👤 Thomas Dr. c/o Philips Corporate Wille
  • 👤 Wolfgang c/o Philips Corporate Hass

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-11-02 18:10
CPC Classifications
G; G06; G06K; G06K19/00; G07; G07F; G07F7/00; G07F7/08; G07F7/10; G07F7/1008; G06F; G06F21/00; G06F21/70; G06F21/71; G06F21/72; G06F21/75; G06F21/755; G06F21/77; G06Q; G06Q20/00; G06Q20/30; G06Q20/34; G06Q20/341; G07F7/0806; G07F7/0813; G07F7/082; H; H04; H04L; H04L9/00; H04L9/002; H04L9/003; H04L9/06; H04L9/0618; H04L9/0625; G06F2207/00; G06F2207/72; G06F2207/7219; H04L2209/00; H04L2209/08; H04L2209/12; H04L2209/125

Claims Analysis

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References Cited (Backward Citations)

US4813024A Cited

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