EP0965902A2
Expired / Lapsed
EP
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Secure data processor with cryptography and tamper detection
Assignee: National Semiconductor Corp
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Filing: 1995-05-05
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Granted: —
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Expires: 2015-05-05
Abstract
Abstract The present invention is embodied in a Secured Processing Unit (SPU) chip, a microprocessor designed especially for secure data processing. By integrating keys, encryption/decryption engines and algorithms in the SPU, the entire security process is rendered portable and easily distributed across physical boundaries. The invention is based on the orchestration of three interrelated systems: (i) detectors, which alert the SPU to the existence, and help characterize the nature, of a security attack; (ii) filters, which correlate the data from the various detectors, weighing the severity of the attack against the risk to the SPU's integrity, both to its secret data and to the design itself; and (iii) responses, which are countermeasures, calculated by the filters to be most appropriate under the circumstances, to deal with the attack or attacks present. The present invention, with wide capability in all three of the detectors, filters and responses, allows a great degree of flexibility for programming an appropriate level of security/policy into an SPU-based application.
Inventors
- 👤 Gordon Force
- 👤 Timothy D. Davis
- 👤 Richard L. Duncan
- 👤 Thomas M. Norcross
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-06 01:29
CPC Classifications
G; G06; G06K; G06K19/00; G06K19/06; G06K19/067; G06K19/07; G06F; G06F21/00; G06F21/70; G06F21/81; G06F21/10; G06F21/109; G06F21/50; G06F21/57; G06F21/572; G06F21/71; G06F21/72; G06F21/725; G06F21/77; G06F21/86; H; H04; H04L; H04L9/00; H04L9/002; H04L9/08; H04L9/0894; H04L9/0897; H04L9/12; G06F2221/00; G06F2221/21; G06F2221/2101; G06F2221/2135; G06F2221/2153; H04L2209/00; H04L2209/56
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
89 words
A secure cryptographic chip for processing and storing sensitive information, including
messages received and generated by the chip and keys used to encrypt and decrypt the
messages, and for securing the information against potential attacks, the chip comprising: (a) a cryptographic engine for performing cryptographic operations on messages using a first
key; (b) one or more detectors for detecting events characteristic of an attack; and (c) a plurality of potential responses to detected events, whereby sensitive information is
unencrypted only on the chip, where it is secure from attack.
Claim 2
Dependent Claim
34 words
A chip according to claim 1 and including a programmable filter for correlating detected
events with one or more operational factors and for selecting and invoking one or more
responses based upon the correlation.
Claim 3
Dependent Claim
29 words
A chip according to claim 1, further comprising a key generator for generating a second key
used by the cryptographic engine to perform cryptographic operations on the first key.
Claim 4
Dependent Claim
61 words
A secure chip according to claim 1 and further comprising: (a) an internal system clock for synchronising functions performed on the chip; and (b) an external signal synchroniser for synchronising to the internal system clock all
asynchronous external signals received by the chip, whereby the chip cannot be placed in an unknown state due to the receipt of asynchronous
external signals.
Claim 5
Dependent Claim
32 words
A secure chip according to claim 4 wherein the external signal synchronizer synchronises
asynchronous external signals by accepting and using the signals only at selected times
determined by the internal system clock.
Claim 6
Dependent Claim
81 words
A chip according to claim 1 and further comprising: (a) an internal bus for transferring information among components of the chip; (b) an input/output port for transferring information between internal components of the chip
and external devices; and (c) a bus monitor for periodically comparing the contents of the input/output port before and
after the transfer of information along the internal bus, whereby the chip can detect unauthorised rerouting, to the input/output port, of sensitive
information transferred along the internal bus.
Claim 7
Dependent Claim
87 words
A chip according to claim 6 wherein the bus monitor compares the contents of the
input/output port before and after: (a) a firs transfer of less than all of the sensitive information desired to be transferred along
the internal bus; and (b) a second transfer of the remaining sensitive information, if no change in the contents of
the input/output port is detected following the first transfer, whereby the chip can effectively prevent the unauthorised rerouting, to the input/output port,
of sensitive information transferred along the internal bus.
Claim 8
Dependent Claim
119 words
A chip according to claim 1 and further comprising: (a) a real time clock controlled by an external clock crystal having a substantially consistent
external clock cycle frequency; (b) an internal system clock for synchronising functions performed on the chip, the internal
system clock cycle frequency within a predetermined range of accuracy; and (c) a clock integrity checking means for causing the chip to perform a reference operations
requiring a predetermined number of internal clock cycles elapsed per actual external clock
cycle during the performance of the reference operation, whether the number of elapsed actual
external clock cycles lies within the range of expected external clock cycles, whereby the chip can detect unauthorised tampering with the external clock frequency.
Claim 9
Dependent Claim
112 words
A chip according to claim 1 and further comprising: (a) a real time clock controlled by an external clock crystal having a substantially consistent
external clock frequency, the real time clock having a counter for counting the number of
elapsed external clock cycles; (b) a rollover detector for detecting whether the real time clock counter rolled over; and (c) a rollover bit, set upon detecting that the real time clock counter rolled over, whereby, if the rolling bit is set during an operation not expected to require a sufficient number
of external clock cycles to cause the counter to roll over, the chip will detect unauthorised
tampering with the external clock frequency.
Claim 10
Dependent Claim
106 words
A chip according to claim 1 and further comprising: (a) a rewritable memory for storing sensitive information; (b) a power loss detector for detecting that the loss of both system and battery power is
imminent; and (c) a VRT bit for indicating the sufficiency of system and battery power following the loading
of sensitive information into the rewritable memory, the VRT bit being set upon the loading
of the sensitive information into the rewritable memory and reset upon the detection of power
loss, whereby the chip can detect the need to save the sensitive information prior to the actual loss
of both system and battery power.
Claim 11
Dependent Claim
37 words
A chip according to claim 10 and further comprising a rewritable memory modification
detector for detecting modification of the rewritable memory, whereby the chip can detect the
need to reload the sensitive information into the rewritable memory.
Claim 12
Dependent Claim
87 words
A chip according to claim 1 wherein the chip comprises: (a) a rewritable memory for storing sensitive information having a substantially constant value; (b) a memory inverter for periodically inverting the contents of each cell of the rewritable
memory; and (c) a memory state bit for indicating whether the contents of each cell of the rewritable
memory are in their actual state, or in the inverted state, whereby the contents of the rewritable memory contain effectively no residual indication of the
constant value of the sensitive information.
References Cited (Backward Citations)
No citation records indexed.
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