EP0932302A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
A CMOS active pixel digital camera
Assignee: Eastman Kodak Co
•
Filing: 1999-01-11
•
Granted: —
•
Expires: 2019-01-11
Abstract
Abstract An image sensor device comprising a silicon substrate having a plurality of CMOS circuit formed thereon, including a pixel array having a plurality of rows and a plurality of columns, a row addressing circuit operatively connected to each the pixel array and the timing control circuit, the row addressing circuit having a row bus that provides address lines to each row in the pixel array, a column addressing circuit, a pixel timing circuit, a timing control logic block, a signal processing circuit, and an interface circuit coupled to external computational means for provision of address and control signals to the sensor device, the interface circuit being operatively coupled the timing control logic, the pixel timing circuit, the row addressing circuit and the column addressing circuit.
Inventors
- 👤 Paul P. c/o Eastman Kodak Company Lee
- 👤 Lawrence J. c/o Eastman Kodak Company Bernstein
- 👤 Robert Michael c/o Eastman Kodak Company Guidash
- 👤 Teh-Hsuang c/o Eastman Kodak Company Lee
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-25 05:03
CPC Classifications
H; H04; H04N; H04N25/00; H04N25/50; H04N25/53; H04N25/70; H04N25/76; H04N25/779; H04N25/7795
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
157 words
An image sensor device comprising: a silicon substrate having a plurality of CMOS circuit formed
thereon ; a pixel array having a plurality of rows and a plurality of columns
formed within the substrate; a timing control logic block formed within the substrate; a row addressing circuit formed within the substrate and
operatively connected to each the pixel array and the timing control circuit, the
row addressing circuit having a row bus that provides address lines to each row in
the pixel array; a column addressing circuit formed within the substrate; a pixel timing circuit formed within the substrate; a signal processing circuit contained within the substrate; and an interface circuit coupled to external computational means for
provision of commands used by the sensor to generate address and control signals
to the sensor device, the interface circuit being operatively coupled the timing
control logic, the pixel timing circuit, the row addressing circuit and the column
addressing circuit.
Claim 2
Dependent Claim
18 words
The invention of claim 1 wherein the timing control logic block
further comprises an electronic shuttering control circuit.
Claim 3
Dependent Claim
26 words
The invention of claim 2 wherein the electronic shuttering
control circuit further comprises a circuit that is programmable responsive to an
input From the interface circuit.
Claim 4
Dependent Claim
49 words
The invention of claim 3 wherein the electronic shuttering
control circuit is responsive to electronic shuttering mode data received from the
interface circuit relating to one of the following: adjustment of electronic
shuttering mode; clearing pixels relative to frame time; integration time for each
frame; or fluorescent light beating.
Claim 5
Dependent Claim
25 words
The image sensor device of claim 1 further comprising a signal
processing circuit coupled to the pixel array to receive data output from the array.
Claim 6
Dependent Claim
19 words
The image sensor device of claim 5 wherein the signal
processing circuit further comprises a correlated double sampling circuit.
Claim 7
Dependent Claim
18 words
The image sensor device of claim 5 wherein the signal
processing circuit Farther comprises a noise reduction circuit.
Claim 8
Dependent Claim
20 words
The image sensor device of claim 7 wherein the noise reduction
circuit further comprises a fixed pattern noise removal circuit.
Claim 9
Dependent Claim
20 words
The image sensor device of claim 5 wherein the signal
processing circuit is further comprises an analog to digital converter.
Claim 10
Dependent Claim
77 words
An semiconductor image sensing device comprising: an imaging array containing a plurality of pixels formed on a
semiconductor substrate; a timing control block formed on the substrate programmable via a
serial communications interface formed on the substrate; means for generating signal required to address and readout the
pixel values formed on the substrate; means form processing the pixel values to form digital words
formed on the substrate; and means for delivering the digital words to external devices.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.