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EP0926715A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Chemical mechanical polishing for isolation dielectric planarization

Assignee: Texas Instruments Inc
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Filing: 1998-12-22
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Granted: —
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Expires: 2018-12-22
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Abstract

Abstract A fabrication method for an integrated circuit structure, comprising the steps of: forming an oxide structure which includes, distributed there-through, a first layer comprising silicon and carbon; and polishing said oxide structure, using a slurry composition which has a selectivity to said first layer of greater than 10 to 1, so that said polishing step smoothly removes said oxide on a first side of said first layer and stops on exposed areas of said first layer; whereby said exposed areas of said first layer define a uniform surface level for said oxide structure. In an embodiment, silicon carbide is used for a hardmask for the isolation dielectric etch and also serves as an etch stop for chemical-mechanical polishing. Alternatively, silicon carbonitride or silicon carboxide can be used.

Inventors

  • 👤 Leif C. Olsen
  • 👤 Leland S. Swanson
  • 👤 Henry L. Edwards

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-11-05 15:29
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/071; H10W20/092; H10P; H10P50/00; H10P50/20; H10P50/24; H10P50/242; H10P95/00; H10P95/06; H10P95/062; H10W10/00; H10W10/01; H10W10/011; H10W10/014; H10W10/10; H10W10/17

Claims Analysis

Total Claims: 9
Claim 1
Independent Claim 93 words
A fabrication method for an integrated circuit structure, comprising the steps of: forming an oxide structure which includes, distributed there-through, a first layer comprising silicon and carbon; and polishing said oxide structure, using a slurry composition which has a selectivity to said first layer of greater than 10 to 1, so that said polishing step smoothly removes said oxide on a first side of said first layer and stops on exposed areas of said first layer; whereby said exposed areas of said first layer define a uniform surface level for said oxide structure.
Claim 2
Dependent Claim 14 words
The fabrication method of Claim 1, wherein said polishing step uses chemical mechanical polishing.
Claim 3
Dependent Claim 22 words
The fabrication method of Claim 1 or Claim 2, wherein said oxide structure fills a trench which extends into a semiconductor material.
Claim 4
Dependent Claim 19 words
The fabrication method of Claim 1, Claim 2 or Claim 3, wherein said first layer consists of silicon carbide.
Claim 5
Dependent Claim 92 words
A fabrication method for an integrated circuit structure, comprising the steps of: (a) providing a substrate which includes a body of semiconductor material; (b) depositing a first layer comprising silicon and carbon over said semiconductor material; (c) forming isolation structures which extend through said first layer into said semiconductor material; (d) filling said isolation structures with a dielectric which also extends over at least a portion of said first layer; (e) performing polishing to planarize said integrated circuit structure; wherein said first layer acts as a polish stop for said polishing step.
Claim 6
Dependent Claim 13 words
The method of Claim 5, wherein said first layer consists of silicon carbide.
Claim 7
Dependent Claim 50 words
The method of Claim 5 or Claim 6, further comprising the step, before said step (b) of: (a1) forming a layer of an oxide over said semiconductor material; (a2) depositing a layer of silicon nitride over said layer of oxide; wherein said first layer directly overlies said silicon nitride layer.
Claim 8
Dependent Claim 19 words
The fabrication method of Claim 5, Claim 6 or Claim 7, wherein said polishing step uses chemical mechanical polishing.
Claim 9
Dependent Claim 36 words
The fabrication method of any one of the preceding Claims, wherein the first layer contains at least one percent as much carbon as silicon, or at least 0.01 or 0.0001 percent as much carbon as silicon.

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