Low jitter timing recovery technique and device for asynchronous transfer mode (ATM) constant bit rate (CBR) payloads

Claim 2

Improved apparatus for a constant bit rate (CBR) payload timing recovery for asynchronous transfer mode (ATM) cells, using a synchronous residual time stamp (SRTS) algorithm, including means for recovering a time stamp at a receiving node, means for comparing the recovered time stamp to a local network derived clock frequency for providing a recovered CBR payload frequency, characterized by means for adaptively filtering buffer fill information for providing said recovered CBR payload frequency in conjunction with said SRTS algorithm.

Claim 3

Improved device for recovering at a receiving node a source clock frequency (10) used at a transmitting node for sending asynchronous transfer mode (ATM) constant bit rate (CBR) cells through a network to the receiving node by reference to a first network derived clock frequency (16) derived at the transmitting node from a network clock, wherein a residual time stamp (RTS) signal (18) provided from said transmitting node via said ATM cells to said receiving node is indicative of a difference frequency between said source clock frequency and said first network derived clock frequency and wherein said RTS is compared at said receiving node to a second network derived clock frequency (28) derived at the receiving node from said network clock for providing a difference signal (30) indicative of said source clock frequency plus or minus a differential frequency (dF) indicative of any difference between said first network derived clock frequency and said second network derived clock frequency wherein the improvement comprises an adaptive filter (74), for use in said receiving node, responsive to said difference signal indicative of said source clock frequency and responsive to a correction signal (112) indicative of a fill level of a buffer (86) of said receiving node for storing payload data (88) of said ATM CBR cells received at the receiving node, for providing said difference signal indicative of said source clock frequency corrected by said adaptive filter.

Claim 4

The improved device of claim 3, wherein said adaptive filter comprises: a comparator (114), responsive to a buffer write address signal and a buffer read address signal, for providing a buffer position signal; a proportional plus integral gain amplifier (118, 120), responsive to said buffer position signal, for providing said correction signal; and an adaptive filter coefficient change device, responsive to said buffer position signal, for providing a control signal, wherein said proportional plus integral gain amplifier is responsive to said control signal for changing parameters thereof.