EP0915479A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Nonvolatile semiconductor memory device and method of reading data therefrom
Assignee: Sony Corp
•
Filing: 1998-11-05
•
Granted: —
•
Expires: 2018-11-05
Abstract
Abstract A memory cell array is constituted with a plurality of memory transistors (M11 to M22) having tunnel insulating films made relatively thick arranged in the form of a matrix, a non-selected column bias voltage of a value between a source voltage and a gate voltage when reading the selected transistor (M11) is supplied to the source and/or drain of a non-selected column memory transistor (M21) arranged in the column not containing the selected memory transistor (M11) in a reverse bias polarity to for example a channel forming region, and a voltage of a value between the voltage to be supplied to the gate of the related selected memory transistor (M11) when reading and a ground voltage supplied to the source of the selected memory transistor (M11). Further, a voltage equivalent to or lower than that for the source of the selected memory transistor (M11) is supplied to the gate of the non-selected row.
Inventors
- 👤 Ichiro c/o Sony Corporation Fujiwara
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 01:15
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/26; H; H10; H10B; H10B41/00; H10B41/30; H10B41/40; H10B43/00; H10B43/30; H10B43/40
Claims Analysis
Total Claims: 53
Claim 1
Independent Claim
209 words
A non-volatile semiconductor memory device comprising: a substrate (1); a plurality of memory transistors (M11 to M22) formed in the vicinity of
the surface of the substrate in a matrix form, each transistor including a
semiconductor channel forming region (1a) formed in the vicinity of the surface of
the substrate (1), a source region (2) formed in the vicinity of the surface of the
substrate (1) and in contact with that channel forming region (1a), a drain region
(4) in contact with the channel forming region (1a) at a distance from the source
region (2), a gate insulating film (6) containing a tunnel insulating film (10)
formed in the channel forming region (1a), a conductive gate electrode (8) formed
on the gate insulating film (6), and a charge storing means formed inside the gate
insulating film (6); and a non-selected column biasing means (20) for supplying a non-selected
bias voltage having a voltage value between a source voltage when reading a data
from the selected memory transistor (M11) and a voltage supplied to the gate of
the selected memory transistor (M11) when reading, to the sources and/or drains
of the non-selected column memory transistors arranged in columns not
containing the selected memory transistor (M11) for reading the data therefrom.
Claim 2
Dependent Claim
56 words
A non-volatile semiconductor memory device as set forth in claim 1,
further comprising a selected memory transistor biasing means for supplying a
voltage between the voltage supplied to the gate of the selected memory transistor
(M11) when reading and a ground voltage to the source of the selected memory
transistor (M11) to set the source voltage.
Claim 3
Dependent Claim
54 words
A non-volatile semiconductor memory device as set forth in claim 2,
further comprising a non-selected row biasing means (22) for supplying a voltage
substantially the same as or lower than the selected memory transistor biasing
means to gates of the non-selected row memory transistors arranged in rows not
containing the selected memory transistor (M11).
Claim 4
Dependent Claim
49 words
A non-volatile semiconductor memory device as set forth in claim 1,
wherein the absolute value of the difference between the voltage supplied by the
non-selected row biasing means (22) and the voltage supplied to the gate of the
selected memory transistor (M11) when reading is not more than 1V.
Claim 5
Dependent Claim
33 words
A non-volatile semiconductor memory device as set forth in claim 1,
wherein said non-selected row biasing means (22) supplies the same voltage to the
sources and drains of the non-selected row memory transistors.
Claim 6
Dependent Claim
35 words
A non-volatile semiconductor memory device as set forth in claim 1,
wherein the channel forming region (1a) of the memory transistor is not depleted
to the center portion when the gate is the ground voltage.
Claim 7
Dependent Claim
52 words
A non-volatile semiconductor memory device as set forth in claim 1,
wherein the channel forming region (1a) of the memory transistor is not depleted
to the center portion or the source region when the ground voltage is supplied to
the gate and a predetermined drain read voltage is supplied to the drain.
Claim 8
Dependent Claim
81 words
A non-volatile semiconductor memory device as set forth in claim 1,
further comprising: a source line (SL1) for commonly connecting the sources of the plurality of
memory transistors in the column direction: a bit line (BL1, BL2) for commonly connecting the drains in the column
direction: and a word line (WL1, WL2) for commonly connecting the gates in the row
direction, and said non-selected row biasing means (22) being connected to said source
line (SL1, SL2) and/or bit line (BL1, BL2).
Claim 9
Dependent Claim
74 words
A non-volatile semiconductor memory device as set forth in claim 2,
further comprising: a source line (SL1, SL2) for commonly connecting the sources of the
plurality of memory transistors in the column direction: a bit line (BL1, BL2) for commonly connecting the drains in the column
direction: and a word line (WL1, WL2) for commonly connecting the gates in the row
direction, said selected memory transistor biasing means being connected to the
source line.
Claim 10
Dependent Claim
76 words
A non-volatile semiconductor memory device as set forth in claim 3,
further comprising: a source line (SLI, SL2) for commonly connecting the sources of the
plurality of memory transistors in the column direction: a bit line (BL1, BL2) for commonly connecting the drains in the column
direction: and a word line (WL1, WL2) for commonly connecting the gates in the row
direction: said selected row biasing means (22) being connected to the word line
(WL1, WL2).
Claim 11
Dependent Claim
123 words
A non-volatile semiconductor memory device as set forth in claim 8,
wherein said source line comprises a sub source line (SSL) to which the source
regions are connected and a main source line (MSL), wherein said bit line
comprises a sub bit line (SBL) to which the drain regions are connected and a
main bit line (BL1, BL2), wherein said memory device further comprises selection transistors (S12,
S22, S11, S21) between the sub source line (SSL) and main source line (MSL)
and between the sub bit line (SBL) and main bit line (BL1, BL2), and wherein the non-selected column bias voltage is supplied through the
selection transistors (S12, S22, S11, S21) to the main source line side and/or the
main bit line side.
Claim 12
Dependent Claim
86 words
A non-volatile semiconductor memory device as set forth in claim 8,
further comprising a plurality of element isolation regions (71) of a line shape in
the bit line direction formed on the surface of the substrate a distance away from
each other, and one of the source line or bit line being connected on one region to be
connected among the source regions or drain regions and is laid in a serpentine
manner on the element isolation regions (71) so as to avoid the other regions.
Claim 13
Dependent Claim
79 words
A non-volatile semiconductor memory device as set forth in claim 12,
wherein the element isolation regions (71) form parallel stripe shapes, self-aligned contact holes are formed in the source regions and drain
regions by side wall insulating layers formed at side walls of the word line, and the one of the source line or bit line laid in a serpentine manner on the
element isolation regions (71) is laid in a serpentine manner while commonly
connecting the other regions.
Claim 14
Dependent Claim
44 words
A non-volatile semiconductor memory device as set forth in claim 1,
wherein said charge storing means does not have conductivity as a plane as a
whole facing the channel forming region when there is no movement of the charge
with at least the outside.
Claim 15
Dependent Claim
28 words
A non-volatile semiconductor memory device as set forth in claim 14,
wherein the charge storing means is at least in the planarly dispersed facing the
channel forming region.
Claim 16
Dependent Claim
46 words
A non-volatile semiconductor memory device as set forth in claim 14,
wherein said gate insulating film (6; 30) includes a tunnel insulating film (10) on
the channel forming region (1a) and a nitride film (12) or an oxynitride film (32)
on the tunnel insulating film (10).
Claim 17
Dependent Claim
58 words
A non-volatile semiconductor memory device as set forth in claim 14,
wherein said gate insulating film (40) includes at least a tunnel insulating film (10)
on the channel forming region (1a) and small particle size conductors (42) with
particle sizes of not more than 10 nanometers formed on the tunnel insulating film
(10) as said charge storing means.
Claim 18
Dependent Claim
239 words
A non-volatile semiconductor memory device comprising: a substrate (1); a plurality of memory transistors (M11 to M22) formed in the vicinity of
the surface of the substrate in a matrix form, each transistor including a
semiconductor channel forming region (1a) formed in the vicinity of the surface of
the substrate, a source region (2) formed in the vicinity of the surface of the
substrate (1) and in contact with that channel forming region (1a), a drain region
(4) in contact with the channel forming region (1a) at a distance from the source
region (2), a gate insulating film (6) containing a tunnel insulating film (10)
formed in the channel forming region, a conductive gate electrode (8) formed on
the gate insulating film (6), and a charge storing means formed inside the gate
insulating film (6); gate electrodes of the plurality of memory elements (M11 to M22) being
connected to a plurality of word lines (WL1, WL2): source regions or drain regions being connected to a common line (BL1,
BL2) in the bit line direction intersecting the word lines (WL1, WL2) in an
electrically insulated state: and a non-selected column biasing means (20) for supplying to source regions
and/or drain regions of the non-selected memory elements having gate electrodes
connected to the selected word line when reading a data via the common line a
voltage by which the related regions become reversely biased with respect to the
channel forming region.
Claim 19
Dependent Claim
55 words
A non-volatile semiconductor memory device as set forth in claim 18,
further comprising a selected element biasing means for supplying to the common
line connected to the source region of the memory element selected (M11) when
reading a voltage of a direction becoming an reverse bias to the channel forming
region of the memory element.
Claim 20
Dependent Claim
59 words
A non-volatile semiconductor memory device as set forth in claim 19,
further comprising a non-selected row biasing means (22) for supplying to the
non-selected word lines a voltage of a polarity becoming a reverse bias to the
channel forming region and substantially the same as or lower than the voltage
supplied to the selected element biasing means when reading.
Claim 21
Dependent Claim
28 words
A non-volatile semiconductor memory device as set forth in claim 18,
wherein the charge storing means is at least in the planarly dispersed facing the
channel forming region.
Claim 22
Dependent Claim
181 words
A non-volatile semiconductor memory device comprising: a substrate (1); a plurality of memory transistors (M11 to M22) formed in the vicinity of
the surface of the substrate (1) in a matrix form, each transistor including a
semiconductor channel forming region (1a) formed in the vicinity of the surface of
the substrate, a source region (2) formed in the vicinity of the surface of the
substrate (1) and in contact with that channel forming region (1a), a drain region
(4) in contact with the channel forming region (1a) at a distance from the source
region (2), a gate insulating film (6) containing a tunnel insulating film (10)
formed in the channel forming region (1a), a conductive gate electrode (8) formed
on the gate insulating film, and a charge storing means formed inside the gate
insulating film (6); and a selected memory transistor biasing means for supplying to the source of
the selected memory transistor (M11) for reading a data a voltage of a value
between the voltage supplied to the gate of the selected memory transistor when
reading and the ground voltage.
Claim 23
Dependent Claim
184 words
A non-volatile semiconductor memory device comprising: a substrate (1); a plurality of memory transistors (M11 to M22) formed in the vicinity of
the surface of the substrate (1) in a matrix form, each transistor including a
semiconductor channel forming region (1a) formed in the vicinity of the surface of
the substrate, a source region (2) formed in the vicinity of the surface of the
substrate (1) and in contact with that channel forming region (1a), a drain region
(4) in contact with the channel forming region (1a) at a distance from the source
region (2), a gate insulating film (6) containing a tunnel insulating film (10)
formed in the channel forming region (1a), a conductive gate electrode (8) formed
on the gate insulating film (6), and a charge storing means formed inside the gate
insulating film (6); and a selected memory transistor biasing means for supplying to the drain of
the selected memory transistor (M11) for reading the information a reading drain
voltage larger than the source voltage and less than or equal to the reading gate
voltage supplied to the gate when reading.
Claim 24
Dependent Claim
30 words
A non-volatile semiconductor memory device as set forth in claim 22,
wherein the memory transistor has a threshold voltage when erasure of a value of
0V or a positive value.
Claim 25
Dependent Claim
24 words
A non-volatile semiconductor memory device as set forth in claim 22,
wherein the thickness of the tunnel insulating film is at least 2.3 nm.
Claim 26
Independent Claim
235 words
A method of reading a data from a non-volatile semiconductor memory
device, said device comprising: a substrate (1); a plurality of memory transistors
(M11 to M22) formed in the vicinity of the surface of the substrate (1) in a matrix
form, each transistor including a semiconductor channel forming region (1a)
formed in the vicinity of the surface of the substrate, a source region (2) formed in
the vicinity of the surface of the substrate (1) and in contact with that channel
forming region (1a), a drain region (4) in contact with the channel forming region
(1a) at a distance from the source region (2), a gate insulating film (6) containing a
tunnel insulating film (10) formed in the channel forming region (1a), a
conductive gate electrode (8) formed on the gate insulating film (6), and a charge
storing means formed inside the gate insulating film (6); said method of reading a data from the non-volatile semiconductor
memory device including a step of supplying a non-selected bias voltage having a
voltage value between a source voltage when reading the selected memory
transistor (M11) and a voltage supplied to the gate of the selected memory
transistor (M11) when reading, to the sources and/or drains of the non-selected
column memory transistors arranged in columns not containing the selected
memory transistor (M11) for reading the information when reading and to thereby
inhibit erroneous reading to non-selected column memory transistors.
Claim 27
Dependent Claim
59 words
A method of reading a data from a non-volatile semiconductor memory
device as set forth in claim 26, further including a step of supplying a voltage
between the voltage supplied to the gate of the selected memory transistor (M11)
when reading and a ground voltage to the source of the selected memory transistor
(M11) to set the source voltage.
Claim 28
Dependent Claim
57 words
A method of reading a data from a non-volatile semiconductor memory
device as set forth in claim 27, further including a step of supplying a voltage
substantially the same as or lower than the selected memory transistor biasing
means to gates of the non-selected row memory transistors arranged in rows not
containing the selected memory transistor (M11).
Claim 29
Dependent Claim
51 words
A method of reading a data from a non-volatile semiconductor memory
device as set forth in claim 26, wherein the absolute value of the difference
between the non-selected column bias voltage and the voltage supplied to the gate
of the selected memory transistor (M11) when reading is not more than 1V.
Claim 30
Dependent Claim
37 words
A method of reading a data from a non-volatile semiconductor memory
device as set forth in claim 26, further including a step of supplying the same
voltage to the sources and drains of the non-selected memory transistors.
Claim 31
Dependent Claim
41 words
A method of reading a data from a non-volatile semiconductor memory
device as set forth in claim 26, wherein the channel forming region of the memory
transistor is not depleted to the center portion when the gate is the ground voltage.
Claim 32
Dependent Claim
59 words
A method of reading a data from a non-volatile semiconductor memory
device as set forth in claim 26, wherein the channel forming region (1a) of the
memory transistor is not depleted to the center portion or the source region when
the ground voltage is supplied to the gate and a predetermined drain read voltage
is supplied to the drain.
Claim 33
Dependent Claim
88 words
A method of reading a data from a non-volatile semiconductor memory
device as set forth in claim 26, wherein the sources of the plurality of memory transistors are commonly connected
by a source line (SL1, SL2) in the column direction, the drains are commonly connected in the column direction by a bit line
(BL1, BL2), the gates are commonly connected in the row direction by a word line
(WL1, WL2), and the voltage is supplied to the non-selected row memory transistors through
said source line and/or bit line.
Claim 34
Dependent Claim
88 words
A method of reading a data from a non-volatile semiconductor memory
device as set forth in claim 27, wherein the sources of the plurality of memory transistors are commonly connected
by a source line (SL1, SL2) in the column direction, the drains are commonly connected in the column direction by a bit line
(BL1, BL2), the gates are commonly connected in the row direction by a word line
(WL1, WL2), and the voltage is supplied to the source of the selected transistor through said
source line (SL1, SL2).
Claim 35
Dependent Claim
89 words
A method of reading a data from a non-volatile semiconductor memory
device as set forth in claim 28, wherein the sources of the plurality of memory transistors are commonly connected
by a source line(SL1, SL2) in the column direction, the drains are commonly connected in the column direction by a bit line
(BL1, BL2), the gates are commonly connected in the row direction by a word line
(WL1, WL2), and the voltage is supplied to the gates of the selected row memory transistors
through said word line (WL1, WL2).
Claim 36
Dependent Claim
127 words
A method of reading a data from a non-volatile semiconductor memory
device as set forth in claim 33, wherein said source line comprises a sub source line (SSL)to which the source
regions are connected and a main source line (MSL), said bit line comprises a sub bit line (SBL) to which the drain regions are
connected and a main bit line (BL1, BL2), said semiconductor device further comprises selection transistors (S12,
S22, S11, S21) between the sub source line (SSL) and main source line (MSL)
and between the sub bit line (SBL) and main bit line (BL1, BL2), and wherein the non-selected column bias voltage is supplied through the
selection transistors (S12, S22, S11, S21) to the main source line side and/or the
main bit line side.
Claim 37
Dependent Claim
100 words
A method of reading a data from a non-volatile semiconductor memory
device as set forth in claim 33, wherein the non-volatile semiconductor memory device is further comprises a
plurality of element isolation regions (71) of a line shape in the bit line direction
formed on the surface of the substrate a distance away from each other, and one of the source line or bit line is connected on one region to be
connected among the source regions or drain regions and is laid in a serpentine
manner on the element isolation regions (71) so as to avoid the other regions.
Claim 38
Dependent Claim
88 words
A method of reading a data from a non-volatile semiconductor memory
device as set forth in claim 37, wherein the plurality of element isolation regions (71) form parallel stripe shapes, self-aligned contact holes are formed on the source regions and drain
regions by side wall insulating layers formed at side walls of the word line, and the one of the source line or bit line laid in a serpentine manner on the
element isolation regions (71) is laid in a serpentine manner while commonly
connecting the other regions.
Claim 39
Dependent Claim
92 words
A method of reading a data from a non-volatile semiconductor memory
device as set forth in claim 26, further including the step of supplying when reading a voltage for setting the source voltage to the
source of the selected memory transistor (M11) and said non-selected column bias
voltage to the non-selected column memory transistors, supplying predetermined voltages to the gate of the selected memory
transistor (M11) and the gates of memory transistors of the non-selected rows, and supplying a predetermined drain read voltage to the drain of the selected
memory transistor (M11).
Claim 40
Dependent Claim
51 words
A method of reading a data from a non-volatile semiconductor memory
device as set forth in claim 26, wherein said charge storing means does not have
conductivity as a plane as a whole facing the channel forming region when there is
no movement of the charge with at least the outside.
Claim 41
Dependent Claim
35 words
A method of reading a data from a non-volatile semiconductor memory
device as set forth in claim 40, wherein the charge storing means is at least in the
planarly dispersed facing the channel forming region.
Claim 42
Dependent Claim
53 words
A method of reading a data from a non-volatile semiconductor memory
device as set forth in claim 40, wherein said gate insulating film (6; 30) includes a
tunnel insulating film (10) on the channel forming region (1a) and a nitride film
(12) or an oxynitride film (32) on the tunnel insulating film (10).
Claim 43
Dependent Claim
65 words
A method of reading a data from a non-volatile semiconductor memory
device as set forth in claim 40, wherein said gate insulating film (40) includes at
least a tunnel insulating film (10) on the channel forming region (1a) and small
particle size conductors (42) with particle sizes of not more than 10 nanometers
formed on the tunnel insulating film (10) as said charge storing means.
Claim 44
Independent Claim
236 words
A method of reading a data from a non-volatile semiconductor memory
device, said device comprising: a substrate (1); a plurality of memory transistors
(M11 to M22) formed in the vicinity of the surface of the substrate in a matrix
form; each transistor including a semiconductor channel forming region (1a)
formed in the vicinity of the surface of the substrate, a source region (2) formed in
the vicinity of the surface of the substrate (1) and in contact with that channel
forming region (1a), a drain region (4) in contact with the channel forming region
(1a) at a distance from the source region (2), a gate insulating film (6) containing a
tunnel insulating film (10) formed in the channel forming region, a conductive
gate electrode (8) formed on the gate insulating film (6), and a charge storing
means formed inside the gate insulating film (6), in said method of reading a non-volatile semiconductor memory device,
source regions and/or drain regions of the non-selected memory elements having
gate electrodes connected to the selected word line when reading among the
plurality of word lines connecting the gate electrodes in common in the row
direction being supplied through a common line in the bit direction intersecting
the word lines in an electrically insulated state and connecting to the source
regions or drain regions a voltage by which the related regions become reversely
biased with respect to the channel forming region.
Claim 45
Dependent Claim
58 words
A method of reading a data from a non-volatile semiconductor memory
device as set forth in claim 44, further comprising a step of supplying to the
common line connected to the source region of the selected memory element when
reading a voltage of a polarity becoming a reverse bias to the channel forming
region of the memory element.
Claim 46
Dependent Claim
64 words
A method of reading a data from a non-volatile semiconductor memory
device as set forth in claim 45, further including a step of supplying to the non-selected
word lines a voltage of a polarity becoming a reverse bias to the channel
forming region and substantially the same as or lower than the voltage supplied to
the source region of the selected element when reading.
Claim 47
Dependent Claim
51 words
A method of reading a data from a non-volatile semiconductor memory
device as set forth in claim 44, wherein said charge storing means does not have
conductivity as a plane as a whole facing the channel forming region when there is
no movement of the charge with at least the outside.
Claim 48
Dependent Claim
33 words
A method of reading a data from a non-volatile semiconductor memory
device as set forth in claim 47, wherein the charge storing means is at least
planarly dispersed facing the channel forming region.
Claim 49
Independent Claim
194 words
A method of reading a data from a non-volatile semiconductor memory
device, said device comprising: a substrate (1); a plurality of memory transistors
(M11 to M22) formed in the vicinity of the surface of the substrate (1) in a matrix
form, each transistor including a semiconductor channel forming region (1a)
formed in the vicinity of the surface of the substrate (1), a source region (2)
formed in the vicinity of the surface of the substrate (1) and in contact with that
channel forming region (1a), a drain region (4) in contact with the channel
forming region (1a) at a distance from the source region (2), a gate insulating film
(6) containing a tunnel insulating film (10) formed in the channel forming region
(1a), a conductive gate electrode (8) formed on the gate insulating film (6), and a
charge storing means formed inside the gate insulating film (6), said method of reading a non-volatile semiconductor memory device
further including a step of supplying the source of the selected memory transistor
for reading the information with a voltage between the voltage supplied to the gate
of the non-selected memory transistor when reading and the ground voltage.
Claim 50
Independent Claim
196 words
A method of reading a data from a non-volatile semiconductor memory
device, said device comprising: a substrate (1); a plurality of memory transistors
(M11 to M22) formed in the vicinity of the surface of the substrate (1) in a matrix
form, each transistor including a semiconductor channel forming region (1a)
formed in the vicinity of the surface of the substrate (1), a source region (2)
formed in the vicinity of the surface of the substrate (1) and in contact with that
channel forming region (1a), a drain region (4) in contact with the channel
forming region (1a) at a distance from the source region (2), a gate insulating film
(6) containing a tunnel insulating film (10) formed in the channel forming region
(1a), a conductive gate electrode (8) formed on the gate insulating film (6); and a
charge storing means formed inside the gate insulating film (6), in said method of reading a non-volatile semiconductor memory device, the drain of the selected memory transistor for reading the information
being supplied with a reading drain voltage larger than the source voltage and less
than or equal to the reading gate voltage supplied to the gate when reading.
Claim 51
Dependent Claim
37 words
A method of reading a data from a non-volatile semiconductor memory
device as set forth in claim 49, wherein the memory transistor has a threshold
voltage when erasing of a value of 0V or a positive value.
Claim 52
Dependent Claim
31 words
A method of reading a data from a non-volatile semiconductor memory
device as set forth in claim 49, wherein the thickness of the tunnel insulating film
is at least 2.3 nm.
Claim 53
Dependent Claim
90 words
A method of reading a data from a non-volatile semiconductor memory
device as set forth in claim 49, further including the step of supplying, when reading a plurality of memory cells in parallel, a voltage
for setting the source voltage to the sources of a plurality of selected memory
transistors, supplying predetermined voltages to the gates of the plurality of selected
memory transistors and the gates of memory transistors of the non-selected rows,
and supplying a predetermined drain read voltage to the drains of the plurality
of selected memory transistors.
References Cited (Backward Citations)
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