EP0905768A1
Expired / Lapsed
EP
⏱️ 0.0 years remaining
A dual damascene process for metal layers and organic intermetal layers
Assignee: Infineon Technologies AG
•
Filing: 1998-08-21
•
Granted: —
•
Expires: 2018-08-21
Abstract
Abstract A process for the manufacture of silicon integrated circuits uses a dual damascene metallization process with an organic intermetal dielectric (14). A pattern to be etched is first etched in a hard mask (16) without exposing the underlying intermetal dielectric (14) and then transferred into the intermetal dielectric (14) on an enlarged scale. <IMAGE>
Inventors
- 👤 Dirk Tobben
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 15:37
CPC Classifications
H; H10; H10P; H10P50/00; H10P50/73; H10W; H10W20/00; H10W20/01; H10W20/071; H10W20/081; H10W20/084; H10W20/088; H10W20/0882
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
92 words
A process for the manufacture of a
semiconductive integrated circuit comprising the steps
of: preparing a semiconductive workpiece to which a
conductive connection is to be provided; providing a layer of an intermetal dielectric
over the top surface of the workpiece; depositing a layer of a hard mask material over
the intermetal dielectric layer; patterning the hard mask layer to form therein
a stepped pattern without exposing the underlying
intermetal dielectric layer; etching the workpiece to transfer the stepped
pattern into the intermetal dielectric; and filling the pattern with a desired metal.
Claim 2
Dependent Claim
26 words
The process of claim 1 in which the stepped
patterning of the hard mask includes separate patterning
of first and second levels in the hard mask.
Claim 3
Dependent Claim
15 words
The process of claim 2 in which the intermetal
dielectric is a silicon-free organic material.
Claim 4
Dependent Claim
11 words
The process of claim 3 in which the
semiconductor is silicon.
Claim 5
Dependent Claim
15 words
The process of claim 4 in which the hard mask
layer is of silicon oxide.
Claim 6
Dependent Claim
23 words
The process of claim 5 in which the hard mask
layer comprises a layer of silicon nitride overlying a
layer of silicon oxide.
Claim 7
Dependent Claim
22 words
The process of claim 2 in which the stepped
pattern includes a relatively narrow deeper portion and a
relatively wide upper portion.
Claim 8
Dependent Claim
39 words
The process of claim 7 in which the etching of
the workpiece to transfer the pattern on an enlarged
scale into the intermetal dielectric uses an etch that
etches preferentially the intermetal dielectric layer
over the hard mask layer.
Claim 9
Dependent Claim
11 words
The process of claim 8 in which the
semiconductor is silicon.
Claim 10
Dependent Claim
16 words
The process of claim 9 in which the intermetal
dielectric layer is a silicon-free organic material.
Claim 11
Dependent Claim
16 words
The process of claim 10 in which the hard mask
comprises a layer of silicon oxide.
Claim 12
Dependent Claim
22 words
The process of claim 11 in which the hard mask
comprises a layer of silicon nitride overlying a layer of
silicon oxide.
Claim 13
Dependent Claim
17 words
The process of claim 12 in which the hard mask
is patterned by an anisotropic fluorine-based etch.
Claim 14
Dependent Claim
31 words
The process of claim 9 in which the transfer of
the metallization pattern in the hard mask to the
metallization pattern in the intermetal dielectric uses
an anisotropic oxygen plasma etch.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.