Semiconductor structure with abrupt doping profile

Claim 2

The structure of claim 1 wherein said second layer comprises a material selected from the group consisting of Si and SiGe.

Claim 3

The structure of claim 1 or 2 wherein said first layer has a thickness in the range from 0.5 to 2 nm.

Claim 4

The structure of any preceding claim wherein said second layer has a concentration change from said first layer into 4nm (40Å) of said second layer of greater than 1 X 10 19 atoms cm -3 .

Claim 5

The structure of any preceding claim further including a third epitaxial layer of semiconductor material having a doping profile with a dopant concentration less than 5 X 10 18 atoms /cm -3 .

Claim 6

The structure of any preceding claim wherein said second epitaxial layer has a thickness of at least 30nm (300Å) and has a doping of phosporus less than 5 X 10 16 atoms /cm -3 for a predetermined thickness after its initial 30nm (300Å) thickness.

Claim 8

The method of claim 7 wherein said step of providing comprises providing a plurality of substrates, each substrate having a major upper surface, and wherein said steps of forming said first and second epitaxial layers are performed with respect to said plurality of substrates.

Claim 9

The method of claim 7 or 8 wherein said step of forming said first epitaxial layer further includes the steps of placing said substrate in a CVD reactor and flowing a germanium containing gas and a dopant containing gas.

Claim 11

The method of claim 10 as dependent on claim 9, wherein said step of adjusting the growth rate further includes the step of changing the flow rate of said germanium containing gas.

Claim 14

The method of claim 13 wherein said step of forming said second epitaxial layer further includes the step of adjusting the flow rate of said dopant containing gas as a function of time.

Claim 15

The method of claim 13 or 14, wherein said step of forming said second epitaxial layer includes after the step of forming said first epitaxial layer, the steps of removing said substrate from said first CVD reactor to a load lock having a controlled atmosphere to prevent oxidation of the surface of said layer, and transferring said substrate to a second CVD reactor having internally exposed surfaces initially free of phosphorus.

Claim 16

The method of claim 13 or 14, wherein said step of forming said second epitaxial layer includes the steps of: removing said substrate from said the CVD reactor to a load lock having a controlled atmosphere to prevent oxidation of the surface of said layer; flowing a silicon containing gas into the CVD having heated surfaces to coat said heated surfaces with a third silicon containing layer to cover said heated surfaces that may contain phosphorus containing layers that may have formed during the formation of said first epitaxial layer; transferring said substrate back into the CVD reactor, and forming a fourth layer on the upper surface of said second epitaxial layer.

Claim 17

The method of claim 16 wherein said step of flowing a silicon containing gas includes the step of flowing the combination of H 2 /SiH 4 /GeH 4 .

Claim 18

A field effect transistor (91) comprising: a single crystal substrate (82) having a source region (87) and a drain region (88) with a channel therebetween and a gate electrode (86) above said channel to control charge in said channel, and a first layer of Ge (80") less than the critical thickness doped with a dopant selected from the group consisting of phosphorus and arsenic and extending through said source and drain regions , characterised in that said first layer is formed directly on said substrate and in that it is positioned below said channel.

Claim 19

The field effect transistor of claim 18 wherein said layer of Ge is in the range from 0.5 to 2nm thick.

Claim 20

The field effect transistor of claim 18 wherein said channel is in a second epitaxial layer selected from the group consisting of Si and SiGe formed over said first layer.

Claim 21

A field effect transistor (102) comprising: a single crystal substrate (95), a first layer (96) of Ge less than the critical thickness doped with a dopant selected from the group consisting of phosphorus and arsenic, a second layer (97) of undoped SiGe epitaxially formed on said first layer, a third layer (98) of strained undoped semiconductor material selected from the group consisting of Si and SiGe, and a source region (103) and a drain region (104) with a channel therebetween, and a gate electrode (106) above said channel to control charge in said channel, characterized in that said first layer (96) is formed directly on said substrate and that it is positioned below said channel.

Claim 22

The field effect Transistor of claim 21 wherein said layer of Ge is in the range from 0.5 to 2nm thick.