EP0875994B1
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EP
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Delta-sigma pulse width modulator
Assignee: HP Inc
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Filing: 1998-03-31
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Granted: 2002-01-23
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Expires: 2018-03-31
Abstract
No abstract record available.
Inventors
- 👤 Richard S. Lewison
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 18:00
CPC Classifications
H; H03; H03K; H03K7/00; H03K7/08; H03M; H03M3/00; H03M3/30; H03M3/322; H03M3/324; H03M3/326; H03M3/328; H03M3/3283; H03M3/50; H03M3/502; H03M3/506
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
186 words
A control,circuit for controlling power delivered to a load with reduced spurious
electromagnetic energy generation, comprising: a delta sigma modulator (201) accepting a first signal and generating a second
signal representing said first signal with a plurality of digital pulses; and a pulse width modulator (205) coupled to said delta sigma modulator,
accumulating said second signal over a first time period, and generating a third signal using an active high protocol or an active low protocol, said third signal being
coupled to the load and having a first magnitude value, said first magnitude value
lasting for a second time period related to said second signal,
said third signal including a third time period greater than and
encompassing said second time period and said third time period
being equal to said first time period, the pulse width modulator
including a delay generator (503) for generating a random time delay signal
to delay a commencement of said second time period from a
commencement of said third time period by a time equal to said time
delay, whereby said delay is set to zero whenever
said pulse protocol transitions.
Claim 2
Dependent Claim
56 words
A control circuit in accordance with claim 1 wherein said pulse width
modulator further comprises: a pulse counter (501) to accumulate a predetermined number of said second
signal plurality of digital pulses; and a waveform generator (505), coupled to said pulse counter, to generate from
said accumulated predetermined number of second signal pulses said third signal.
Claim 3
Dependent Claim
164 words
A control circuit in accordance with claim 2 wherein said pulse width
modulator further comprises a pulse width indicator (507) to indicate when an
accumulation of second signal pulses create said third signal second time period
lasting for greater than 50% of said third time period and further comprises a divide-by-two
(901) coupled to a fourth signal representing said third time period to generate
a halved fourth signal; and a comparator (903) coupled to said divide-by-two to accept said halved fourth
signal, coupled to said pulse counter to accept said accumulated second signal, and
outputting a two state signal representing with a first state that said accumulated
second signal is greater than said halved fourth signal, thereby indicating that said
second time period exceeds 50% of said third time period, and representing with a
second state that said accumulated second signal is less than said halved fourth signal,
thereby indicating that said second time period does not exceed 50% of said third time
period.
Claim 4
Dependent Claim
150 words
A control circuit in accordance with claim 3 wherein said pulse width
modulator further comprises a pulse protocol inverter (507) coupled to said pulse
width indicator to transform said third signal from an active high first magnitude
value protocol to an active low first magnitude value protocol and wherein said pulse
protocol converter further comprises an adder (909), coupled to said pulse counter, for
subtracting said accumulated second signal from a fourth signal representing said
third time period thereby generating a difference signal; and a multiplexer (905) coupled to said pulse counter for receiving said accumulated
second signal, coupled to said adder for receiving said difference signal, and coupled
to said pulse width indicator to receive an indication when said second time period
exceeds 50% of said third time period and switching said multiplexer output from said
accumulated second signal to said difference signal upon said exceeding of 50% .
Claim 5
Dependent Claim
85 words
A control circuit in accordance with claim 4 further comprising: a delay generator disable (722) coupled to said delay generator and said pulse
protocol inverter for carrying out the setting of the delay to zero said first time
period has an active high first magnitude value protocol and is immediately followed
by a following first period having an active low first magnitude value protocol,
thereby reducing the number of transitions from said first magnitude value to a second
magnitude value during said following first period.
Claim 6
Dependent Claim
58 words
A control circuit in accordance with claim 4 wherein said pulse width
modulator further comprises: an adder (731) accepting a bus output from said pulse protocol inverter; and a ones value generator (745) coupled to said adder to increase a digital signal
present on said bus output by a value of one for rounding of said digital signal.
Claim 7
Independent Claim
170 words
A method of controlling power delivered to a load with reduced spurious
electromagnetic energy generation, comprising the steps of: accepting a first signal input to a delta sigma modulator; generating a second signal representing said first signal with a plurality of
digital pulses ; accumulating said second signal over a first time period; generating a third signal setting a third time period equal to said first time period; using an active high protocol or an active low protocol, said third signal being coupled to the load and having a first magnitude
value, said first magnitude value lasting for a second fine period related to said
second signal, said third signal including said third time period which is greater
than and which encompasses said second time period; and generating a random time delay signal to delay a commencement
of said second time period from a commencement of said third time
period by a time equal to said time delay, whereby said delay is
set to zero whenever said pulse protocol transitions.
Claim 8
Dependent Claim
66 words
A method in accordance with the method of claim 7 further comprising the
steps of: accumulating a predetermined number of said second signal plurality of digital
pulses; generating, from said accumulated predetermined number of second signal
pulses, said third signal, and indicating when an accumulation of second signal pulses create said third
signal second time period lasting for greater than 50% of said third time period.
Claim 9
Dependent Claim
151 words
A method in accordance with the method of claim 8 further comprising the
steps of: transforming said third signal from an active high first magnitude value
protocol to an active low first magnitude value protocol; subtracting said accumulated second signal from a fourth signal representing
said third time period thereby generating a difference signal; outputting said accumulated second signal; receiving an indication when said second time period exceeds 50% of said
third time period; outputting said accumulated second signal to said difference signal upon said
exceeding of 50%; carrying out the setting of the time delay signal to be zero when said first time period has
an active high first magnitude value protocol and is immediately followed by a
following first period having an active low first magnitude value protocol, thereby
reducing the number of transitions from said first magnitude value to a second
magnitude value during said following first period.
Claim 10
Dependent Claim
49 words
A method in accordance with the method of claim 9 further comprising
the steps of: accepting a bus output from said pulse protocol inverter; and adding a value of one to said bus to increase a digital signal present on said
bus output for rounding of said digital signal.
References Cited (Backward Citations)
No citation records indexed.
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