Multi-scan video timing generator for format conversion

Claim 2

The format converter of claim 1, wherein said display timing controller further comprises: clock generation means for generating a display main clock signal; a lock event controller for generating a lock event signal at a predetermined instant of each frame of said digital video input signal; display synchronizer means for generating a display horizontal lock event signal and a display vertical lock event signal for controlling synchronization between said digital video input signal and said digital video output signal based on said lock event signal and said operating mode information; and display timing generator means for generating timing signals synchronized to said horizontal and vertical lock event signals to control said display processor means in accordance with said operating mode information.

Claim 3

The format converter of claim 2, wherein said clock generation means further comprises: a free running clock for generating a free running clock signal which is not synchronized to said digital input video signal; phase lock loop means for receiving an input clock signal derived from said digital input video signal and in response generating a synthesized clock signal which is a ratio multiple of said input clock signal; and a clock selector for selecting one of said free running clock signal or said synthesized clock signal for output as a display main clock signal.

Claim 4

The format converter of claim 3, wherein said lock event controller further comprises: a programmable control register for generating a predetermined horizontal lock event value and a predetermined vertical lock event value based on said operating mode information; a horizontal pixel event counter for counting successive cycles of said input clock signal relative to each of a succession of horizontal synchronization pulses of said digital input video signal and in response generating a horizontal pixel count value; a horizontal pixel event comparator for comparing said horizontal pixel count value with said predetermined horizontal lock event value, and when said horizontal pixel count value is equal to said predetermined horizontal lock event value then generating a horizontal lock event pulse; a vertical line counter for counting successive ones of said horizontal synchronization pulses relative to a succession of input vertical synchronization pulses of said digital input video signal and in response generating a vertical line count value; a vertical line event comparator for comparing said vertical line count value with said predetermined vertical lock event value, and when said vertical line count value is equal to said predetermined vertical lock event value then generating a vertical lock event pulse; a lock event generator for generating a lock event pulse when said horizontal lock event pulse and said vertical lock event pulse coincide; and a lock event selector for selecting one of either a frame synchronization signal derived from said digital input video signal, said input clock signal, or said lock event pulse for output as said lock event signal based on said operating mode information.

Claim 5

The format converter of claim 4, wherein said display synchronizer further comprises circuitry for receiving said input clock signal, said display main clock signal, said lock event signal and said operating mode information, and in response generating said display horizontal and vertical lock event signals and a run enable signal wherein: (i) in the event said operating mode information indicates a free run operating mode, the display horizontal and vertical lock event signals are suppressed so that there is no synchronization between said digital input video signal and said digital output video signal, and said run enable signal is synchronized to said display main clock signal for enabling and disabling said display timing generator; (ii) in the event said operating mode indicates a clock synchronized mode of operation, the display horizontal and vertical lock event signals are synchronized to said lock event signal initially at start up, and said run enable signal is synchronized to said display main clock signal thereafter for enabling and disabling said display timing generator; (iii) in the event said operating mode indicates a frame synchronized mode of operation, the display horizontal and vertical lock event signals are synchronized to said lock event signal on a per frame basis of the digital input video signal, and said run enable signal is synchronized to said display main clock signal for enabling and disabling said display timing generator; and (iv) in the event said operating mode indicates a line synchronized mode of operation, the display horizontal and vertical lock event signals are synchronized to said lock event signal on a per line and per frame basis of the digital input video signal, and said run enable signal is synchronized to said display main clock signal for enabling and disabling said display timing generator.

Claim 6

The format converter of claim 5 wherein said display timing generator further comprises: a horizontal controller for receiving said display main clock signal, said operating mode information, said horizontal lock event signal and said run enable signal and in response generating a horizontal end of frame signal for indicating transitions between successive lines of said digital output video signal, a display horizontal synchronization signal for driving said display, and an output enable signal for enabling said display; and a vertical controller for receiving said display main clock signal, said operating mode information, said vertical lock event signal, said run enable signal and said horizontal end of frame signal and in response generating a display vertical synchronization signal for driving said display, and a display vertical enable signal for application to sad horizontal controller in connection with generating said output enable signal.

Claim 7

The format converter of claim 1 wherein said digital input video signal is an interlaced signal and said digital output video signal is a progressive scan signal.

Claim 8

The format converter of claim 1 wherein said digital input video signal is a progressive scan signal and said digital output video signal is also a progressive scan signal.

Claim 9

A display timing controller for deriving synchronization and control information from a digital video input signal based and in response controlling operation of said display processor to generate a digital video output signal for display at a viewable display resolution, pixel rate and line rate different from that of said digital video input signal, comprising: clock generation means for generating a display main clock signal; a lock event controller for generating a lock event signal at a predetermined instant of each frame of said digital video input signal; display synchronizer means for generating a display horizontal lock event signal and a display vertical lock event signal for controlling synchronization between said digital video input signal and said digital video output signal based on said lock event signal; and display timing generator means for generating timing signals synchronized to said horizontal and vertical lock event signals to control said display processor to generate said digital video output signal for display at said viewable display resolution, pixel rate and line rate.