EP0865178A2
Expired / Lapsed
EP
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Apparatus for providing error correction data in a digital transfer system
Assignee: Harris Corp
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Filing: 1998-02-17
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Granted: —
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Expires: 2018-02-17
Abstract
Abstract An apparatus for providing error correction data in a digital data transfer system, which receives a clock signal to provide a first signal. Information data is received and a second signal is provided using the information data, which is received in groups each having a first predetermined number of elements. A plurality of aROMs provide Galois Field multiples in look-up tables, that are addressed using the first signal to provide a first address component and using the second signal to provide a second address component. The error correction data is in groups each having a second predetermined number of elements. A RAM is accessible by a Trellis encoder and has an array for holding the information data elements and error correction data elements.
Inventors
- 👤 Edwin Ray Twitchell
- 👤 Paul H. Mizwicki
- 👤 Joseph Lee Seccie
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 19:30
CPC Classifications
H; H04; H04L; H04L1/00; H04L1/004; H04L1/0056; H04L1/0057; H04L1/0045; H04L1/0052; H04L1/0059; H04L1/006; H04L1/0064; H04L1/0065; H04L1/0071
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
112 words
An apparatus for providing error correction data in a digital data transfer system, said
apparatus comprising, means for receiving a clock signal, means for providing a first signal using
the clock signal, means for receiving information data, means for providing a second signal using
the information data, memory means for holding values, said memory means having a plurality of
addressable memory locations, each memory location containing a value, means for addressing said
memory means using the first signal to provide a first address component and using the second
signal to provide a second address component,and mathematics means for performing mathematics
utilizing a value from said memory means to generate error correction data.
Claim 2
Dependent Claim
112 words
An apparatus as claimed in claim 1, wherein the information data is received in
groups which each have a first predetermined number of elements, and the error correction data
is generated in groups each having a second predetermined number of elements, including memory
means, accessible by a portion of said digital data transfer system other than said apparatus, for
holding the information data elements and the error correction data elements, said accessible
memory means includes memory array means having a plurality of array locations, each array
location for holding an element, the number of array locations is equal to an integer multiple of the
sum of the first and second predetermined numbers.
Claim 3
Dependent Claim
162 words
An apparatus as claimed in claim 2, including means for providing control signals
using the clock signal, memory array means, having a plurality of array locations, for holding the
information data elements and the error correction data elements, means for sending information
data elements and error correction data elements to said memory array means in third groups, and
means for controlling said means for sending in response to a control signal from said means for
providing control signals to cause a first array location of said memory array means to always
receive a first element of one of the third groups of the information data elements and error
correction data elements, including means for providing counter signals using the clock signal,
memory array means, having a plurality of array locations, for holding the information data and the
error correction data, means for sending the information data and error correction data to said
memory array means using the counter signals to determine addresses.
Claim 4
Dependent Claim
126 words
An apparatus as claimed in claim 3, wherein said means for providing counter
signals includes at least two modula counters for providing modula counter signals, said means for
sending includes a decoder means for decoding one of the modula counter signals for an address
portion, said memory array means is accessible by a portion of said digital data transfer system other
than said apparatus and is accessed by the other portion of said system to retrieve data using at least
one of the counter signals, preferably said memory array means including means for placing
sequentially sent elements into said array in correspondence with the determined array addresses
to permit an interleaving of elements upon retrieval of elements from said memory array means in
a sequential progression.
Claim 5
Independent Claim
69 words
An apparatus as claimed in any one of claims 1 to 4, including memory means,
accessible by a portion of said digital data transfer system other than said apparatus, for storing the
information data and the error correction data, means for sending the information data to said
accessible memory means for storage therein, and means for sending the error correction data to
said accessible memory means for storage therein.
Claim 6
Independent Claim
52 words
An apparatus as claimed in any one of claims 1 to 5, wherein said alternate sending
is during a time period for sending a portion of the current group of information data elements, and
the number of elements in the portion of information data elements is equal to the second
predetermined number.
Claim 7
Dependent Claim
127 words
An apparatus as claimed in claim 1 including means for receiving information data,
the information data being received in groups which each have a first predetermined number of
elements, means for generating error correction data in response to the information data, the error
correction data being in groups each having a second predetermined number of elements, and
memory means, accessible by a portion of said digital data transfer system other than said apparatus,
for holding the information data elements and the error correction data elements, said accessible
memory means including memory array means having a plurality of array locations, each array
location for holding an element, the number of array locations being equal to an integer multiple
of the sum of the first and second predetermined numbers.
Claim 8
Dependent Claim
95 words
An apparatus as claimed in claim 15, including means for receiving a clock signal,
means for providing a first signal using the clock signal, means for providing a second signal using
the information data, memory means having a plurality of addressable memory locations for holding
values, and means for addressing said value holding memory means using the first signal to provide
a first address component and using the second signal to provide a second address component, said
means for generating using the values from said value holding memory means to generate the error
correction data.
Claim 9
Independent Claim
104 words
An apparatus as claimed in any one of claims 1 to 8, including means for receiving
a clock signal, means for providing counter signals using the clock signal, said accessible array
means including memory array means having a plurality of array locations for holding the
information data and the error correction data, including means for sending the information data
elements and error correction data elements to said memory array means using the counter signals
to determine addresses, said memory array means is accessible by the other portion of said digital
data transfer system to retrieve data using at least one of the counter signals.
Claim 10
Independent Claim
126 words
An apparatus as claimed in any one of claims 1 to 9, wherein said alternate sending
is during a time period for sending a portion of the current group of information data elements, and
the number of elements in the portion of information data elements is equal to the second
predetermined number, in which the error correction data elements sent during said alternate
sending are of a group of error correction elements which correspond to a previous group of
information data elements, including means for receiving a clock signal and means for providing
a counter signal using the clock signal, said memory array means is accessible by the other portion
of said digital transfer system to retrieve data using at least one of the counter signals.
Claim 11
Independent Claim
297 words
An apparatus for providing error correction data in a digital data transfer system, said
apparatus comprising, means for receiving a clock signal, means for providing clock-based signals
using the clock signal, means for receiving information data elements in first groups, means for
generating error correction data elements using the information data elements and a clock-based
signal from said means for providing clock-based signals, the error correction data elements being
in second groups, memory means, including memory array means having a plurality of array
locations, for holding the information data elements and the error correction data elements, means
for sending information data and error correction data elements to said accessible memory means
in third groups, means for controlling said means for sending in response to a clock-based signal
from said means for providing clock-based signals to cause a first array location of said memory
array means to always receive a first element of one of the third groups of the information data and
error correction data, said means for providing clock-based signals includes counter means for
providing a counter signal using the clock signal, said apparatus further including means for
providing a data-based signal using the information data, memory means having a plurality of
addressable memory locations for holding, and means for addressing said value holding memory
means using the counter signal to provide a first address component and using the data based signal
to provide a second address component, the error correction data is generated using the values from
said value holding memory means, said means for providing clock-based signals includes means
for providing control signals using the clock signal, said means for sending information data and
error correction data elements send elements to said memory array means in third groups in
response to a control signal.
References Cited (Backward Citations)
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