EP0862292A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Method of detecting signal degradation fault conditions within sonet and SDH signals
Assignee: Nokia Canada Inc
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Filing: 1998-02-11
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Granted: —
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Expires: 2018-02-11
Abstract
Abstract In a method of detecting signal degradation conditions in synchronous digital signals, the error monitors first detect the presence and/or absence of a particular bit error ratio by integrating received parity errors over time. Subsequently a monitor client reacts to notifications from bit error rate monitors that the state of the presence/absence of specific bit error ratios has changed to generate an alarm condition when appropriate.
Inventors
- 👤 Dan Burke
- 👤 Alan Jennings
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-01 13:08
CPC Classifications
H; H04; H04J; H04J3/00; H04J3/02; H04J3/14; H04L; H04L1/00; H04L1/20; H04Q; H04Q11/00; H04Q11/04; H04Q11/0428; H04Q11/0478; H04J2203/00; H04J2203/0001; H04J2203/0057; H04J2203/006
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
77 words
A method of detecting signal degradation conditions in synchronous digital
signals, characterized in that it comprises the steps of detecting the presence and/or
absence of particular bit error ratios by integrating received parity errors over time in a
plurality of bit error monitors, and reacting to notifications from bit error rate monitors
that the state of the presence/absence of specific bit error ratios has changed to take a
predetermined action depending on the state of the monitors.
Claim 2
Dependent Claim
21 words
A method as claimed in claim 1, characterized in that said predetermined action is
the raising or clearing of an alarm.
Claim 3
Dependent Claim
29 words
A method as claimed in claim 1 or 2, characterized in that the bit error monitors
generate notifications whenever they detect a crossing of their respective parity count
threshold.
Claim 4
Independent Claim
42 words
A method as claimed in any one of claims 1 to 3, characterized in that each
monitor includes a queue of parity count samples that is used to integrate the number of
errors that have occurred over a fixed period of time.
Claim 5
Dependent Claim
21 words
A method as claimed in claim 4, characterized in that the number of errors is
integrated using a sliding window technique.
Claim 6
Dependent Claim
49 words
A method as claimed in claim 5, characterized in that each time a new error count
sample is received, the value at the head of the sample queue is removed and subtracted
from the total number of errors that have been accumulated over the width of the
integration window.
Claim 7
Independent Claim
52 words
A method as claimed in any one of claims 1 to 6, characterized in that at least
some of said monitors are linked so that at least one of said linked monitors receives its
parity count sample from another said linked monitor at n times the rate of said another
linked monitor.
Claim 8
Dependent Claim
69 words
An appararus for detecting signal degradation conditions in synchronous digital
signals, characterized in that it comprises a plurality of monitors for detecting the
presence and/or absence of particular bit error ratios by integrating received parity errors
over time; and a bit error rate monitor client responsive to outputs from said plurality of
monitors to take a predetermined action depending on the state of said plurality of bit
error monitors.
Claim 9
Dependent Claim
21 words
An apparatus as claimed in claim 8, characterized in that said predetermined
action is the raising or clearing of an alarm.
Claim 10
Dependent Claim
29 words
An apparatus as claimed in claim 8 or 9, characterized in that the bit error
monitors generate notifications whenever they detect a crossing of their respective parity
count threshold.
Claim 11
Dependent Claim
42 words
An appararus as claimed in any one of claims 8 to 10, characterized in that each
monitor includes a queue of parity count samples, and an integrator for integrating the
number of errors that have occurred over a fixed period of time.
Claim 12
Dependent Claim
17 words
An apparatus as claimed in claim 11, characterized in that said integrator uses a
sliding window technique.
Claim 13
Dependent Claim
51 words
An apparatus as claimed in claim 12, characterized in that each time a new error
count sample is received, said integrator removes the value at the head of the sample
queue and subtracts it from the total number of errors that have been accumulated over the
width of the integration window.
Claim 14
Independent Claim
52 words
An apparatus as claimed in any one of claims 8 to 13, characterized in that at least
some of said monitors are linked so that at least one of said linked monitors receives its
parity count sample from another said linked monitor at n times the rate of said another
linked monitor.
Claim 15
Independent Claim
50 words
An apparatus as claimed in any one of claims 8 to 14, characierized in that each
said monitor includes a state machine that keeps track of whether the monitor is currently
detecting a bit error ratio that is either equal to or greater than its currently monitored bit
error ratio.
References Cited (Backward Citations)
No citation records indexed.
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