Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
479 words
A spread-spectrum receiver for a code-division
multiple access (CDMA) communication system, comprising: a radio circuit (12; 32) for converting a high
frequency signal received by an antenna (11; 31) into a
base-band signal through frequency conversion and
quadrature detection; a timing control circuit (13; 33) for detecting
timings on a plurality of paths through search processing
to thereby generate first and second replica code
timing indicating signals, a timing pulse, and first and
second delay time indicating signals; a first replica code generator (14 1 ; 34 1 ) for
generating a first replica code at a timing indicated by
said first replica code timing indicating signal supplied
from said timing control circuit (13; 33); a second replica code generator (14 2 ; 34 2 ) for
generating a second replica code at a timing indicated by
said second replica code timing indicating signal supplied
from said timing control circuit (13; 33), said
second replica code being the same as said first replica
code; a first correlator (15 1 ; 35 1 ) for determining a
correlation value of said base-band signal and said first
replica code supplied from said first replica code generator
(14 1 ; 34 1 ); a second correlator (15 2 ; 35 2 ) for determining
a correlation value of said base-band signal and said
second replica code supplied from said second replica
code generator (14 2 ; 34 2 ); a first synchronous detector (16 1 ; 36 1 ) for
outputting a first symbol signal through synchronous
detection of an output signal of said first correlator
(15 1 ; 35 1 ); a second synchronous detector (16 2 ; 36 2 ) for
outputting a second symbol signal through synchronous
detection of an output signal of said second correlator
(15 2 ; 35 2 ); a first timing adjusting buffer (17 1 ; 37 1 ) for
latching said first symbol signal outputted from said
first synchronous detector (16 1 ; 36 1 ) in response to said
timing pulse supplied from said timing control circuit
(13; 33), and outputting said first symbol signal as
latched with a delay time indicated by said first delay
time indicating signal outputted from said timing control
circuit (13; 33); a second timing adjusting buffer (17 2 ; 37 2 ) for
latching said second symbol signal outputted from said
second synchronous detector (16 2 ; 36 2 ) in response to
said timing pulse supplied from said timing control
circuit (13; 33), and outputting said second symbol
signal as latched with a delay time indicated by said
second delay time indicating signal outputted from said
timing control circuit (13; 33); and a RAKE combining circuit (18; 38) for synthesizing
output signals from said first timing adjusting
buffer (17 1 ; 37 1 ) and said second timing adjusting buffer
(17 2 ; 37 2 ).
Claim 2
Dependent Claim
35 words
A spread-spectrum receiver according to claim
1, wherein said first and second delay time indicating
signals indicate delay times for said first and second
timing adjusting buffers (17; 37) on a chip period basis,
respectively.
Claim 3
Dependent Claim
181 words
A spread-spectrum receiver according to claim
2, wherein said first timing adjusting buffer includes: plural stages of first latch circuits (21 11 to
21 18 ) disposed between said first synchronous detector
(16 1 ) and said RAKE combining circuit (18); and a plurality of first switches (22 11 to 22 18 )
disposed between output terminals of said plural stages
of first latch circuits (21 11 to 21 18 ) and said RAKE
combining circuit (18), respectively, and turned on/off
under the control of said first delay time indicating
signal, and said second timing adjusting buffer (17 2 ; 37 2 )
includes: plural stages of second latch circuits (21 21 to
21 28 ) disposed between said second synchronous detector
(16 2 ) and said RAKE combining circuit (18); and a plurality of second switches (22 21 to 22 28 )
disposed between output terminals of said plural stages
of second latch circuits (21 21 to 21 28 ) and said RAKE
combining circuit (18), respectively, and turned on/off
under the control of said second delay time indicating
signal.
Claim 4
Dependent Claim
40 words
A spread-spectrum receiver according to claim
2, wherein said timing control circuit (13) generates
said first and second delay time indicating signals on
the basis of a delay profile obtained by using a long
code longer than one symbol period.
Claim 5
Dependent Claim
45 words
A spread-spectrum receiver according to claim
1, wherein said timing pulse has the same period as the
symbol period, and said first and second delay time indicating
signals indicate delay times for said first and second
timing adjusting buffers on a symbol period basis, respectively.
Claim 6
Dependent Claim
178 words
A spread-spectrum receiver according to claim
5, wherein said first timing adjusting buffer includes: plural stages of first latch circuits (41 11 to
41 13 ) disposed between said first synchronous detector
(36 1 ) and said RAKE combining circuit (38); and a plurality of first switches (42 11 to 42 13 )
disposed between output terminals of said plural stages
of first latch circuits (41 11 to 41 13 ) and said RAKE
combining circuit (38), respectively, and turned on/off
under the control of said first delay time indicating
signal, and said second timing adjusting buffer (37 2 ) includes: plural stages of second latch circuits (41 21 to
41 23 ) disposed between said second synchronous detector
(36 2 ) and said RAKE combining circuit (38); and a plurality of second switches (42 41 to 42 23 )
disposed between output terminals of said plural stages
of second latch circuits (41 21 to 41 23 ) and said RAKE
combining circuit (38), respectively, and turned on/off
under the control of said second delay time indicating
signal.
Claim 7
Dependent Claim
40 words
A spread-spectrum receiver according to claim
5, wherein said timing control circuit (33) generates
said first and second delay time indicating signals on
the basis of the delay profile obtained by using a long
code longer than one symbol period.