EP0851427A2
Expired / Lapsed
EP
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Memory system including an on-chip temperature sensor for regulating the refresh rate of a dram array
Assignee: LSI Corp
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Filing: 1997-12-17
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Granted: —
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Expires: 2017-12-17
Abstract
Abstract A DRAM memory array including a temperature sensor for adjusting a refresh rate depending upon temperature. The DRAM memory array includes a plurality of memory cells, each configured to allow storage and retrieval of more than two discrete memory states. A refresh circuit is coupled to the memory array for periodically refreshing the discrete storage state of each memory cell. The temperature sensor is situated on the same semiconductor die upon which the memory array is fabricated, and generates a signal indicative of the temperature of the semiconductor die. A control circuit receives the signal from the temperature sensor and responsively generates a refresh rate signal which is provided to control the refresh rate of the refresh circuit. In one specific implementation, a ROM look-up table is coupled to the control circuit and includes a plurality of entries which indicate the desired refresh rates for particular temperatures. By controlling the refresh rate dependent upon the temperature of the semiconductor die, proper state retention is ensured within each of the memory cells while allowing performance to be optimized.
Inventors
- 👤 Swamy V. Irrinki
- 👤 Ashok Kapoor
- 👤 Raymond Leung
- 👤 Alex Owens
- 👤 Thomas R. Wik
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-28 00:13
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/04; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/406; G11C11/40626; G11C11/56; G11C11/565; G11C16/00; G11C16/02; G11C16/06; G11C16/34; G11C16/3418; G11C16/3431
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
103 words
A memory circuit comprising: a memory array including a plurality of memory cells; a refresh circuit coupled to said memory array and configured to refresh said
plurality of memory cells; a temperature sensor for generating a temperature signal indicative of a
temperature; and a control circuit coupled to said temperature sensor and to said refresh circuit,
wherein said control circuit is configured to generate a refresh rate signal
dependent upon said temperature signal generated by said temperature
sensor; wherein said refresh circuit is configured to vary a rate of said refresh of said
plurality of memory cells depending upon said refresh rate signal.
Claim 2
Dependent Claim
48 words
The memory circuit as recited in Claim 1 further comprising a look-up table unit
coupled to said control circuit, wherein said look-up table unit is configured to store a
plurality of entries, wherein each of said plurality entries indicates a desired refresh rate
for a particular corresponding temperature.
Claim 3
Dependent Claim
18 words
The memory circuit as recited in Claim 2 wherein said look-up table unit includes a
read only memory.
Claim 4
Dependent Claim
40 words
The memory circuit as recited in Claim 1 further comprising an address decode unit
coupled to said memory array, wherein said address decode unit is configured to select a
designated row of said memory array depending upon an address signal.
Claim 5
Dependent Claim
25 words
The memory circuit as recited in Claim 1 further comprising a read/write logic unit
configured to enable read and write operations of said memory array.
Claim 6
Dependent Claim
20 words
The memory circuit as recited in Claim 1, wherein said refresh circuit decreases said
refresh rate as said temperature increases.
Claim 7
Dependent Claim
25 words
The memory circuit as recited in Claim 1 wherein said temperature sensor is situated
on a semiconductor die of which said memory array is fabricated.
Claim 8
Dependent Claim
26 words
The memory circuit as recited in Claim 1 wherein each of said plurality of memory
cells in configured to store at least three discrete logic values.
Claim 9
Independent Claim
37 words
A method for refreshing memory cells in a memory circuit comprising: sensing a temperature; generating a signal indicative of said temperature; varying a refresh rate of said memory cells depending upon said signal indicative
of said temperature.
Claim 10
Dependent Claim
31 words
The method for refreshing memory cells in a memory circuit as recited in Claim 9
further comprising accessing a ROM look-up table to determine a desired refresh rate for
said temperature.
Claim 11
Dependent Claim
34 words
The method for refreshing memory cells in a memory circuit as recited in Claim 9
further comprising sensing one of more than two discrete logic states within each of said
plurality of memory cells.
Claim 12
Dependent Claim
32 words
The method for refreshing a plurality of memory cells in a memory circuit as recited
in Claim 9 further comprising increasing said refresh rate in response to a decrease in said
temperature.
Claim 13
Dependent Claim
223 words
A memory circuit comprising: a memory array including a plurality of memory cells, wherein each of said
memory cells includes: a storage transistor with a first terminal, a second terminal, and a gate, said
first terminal coupled to a predetermined voltage; a read transistor coupled to said second terminal, said read transistor
configured to conduct a current through said storage transistor
when a read signal is asserted; and a write transistor coupled to said gate, said write transistor configured to
store a charge on said gate of said storage transistor when a write
signal is asserted; an analog-to-digital converter coupled to detect a value indicative of a voltage
across said storage transistor, wherein said analog to digital converter is
configured to convert said value to one of at least three distinct digital
values; a refresh circuit coupled to said memory array and configured to refresh said
plurality of memory cells; a temperature sensor for generating a temperature signal indicative of a
temperature; and a control circuit coupled to said temperature sensor and to said refresh circuit,
wherein said control circuit is configured to generate a refresh rate signal
dependent upon said temperature signal generated by said temperature
sensor; wherein said refresh circuit is configured to vary a rate of said refresh of said
plurality of memory cells depending upon said refresh rate signal.
Claim 14
Dependent Claim
48 words
The memory circuit as recited in Claim 13 further comprising a look-up table unit
coupled to said control circuit, wherein said look-up table unit is configured to store a
plurality of entries, wherein each of said plurality entries indicates a desired refresh rate
for a particular corresponding temperature.
Claim 15
Dependent Claim
18 words
The memory circuit as recited in Claim 14 wherein said look-up table unit includes a
read only memory.
Claim 16
Dependent Claim
32 words
The memory circuit as recited in Claim 13 wherein said analog-to-digital converter
comprises a plurality of comparators, each coupled to compare said input voltage to one
of a plurality of reference voltages.
Claim 17
Dependent Claim
38 words
The memory circuit as recited in Claim 13 further comprising a data line driver
coupled to receive one of said distinct digital values, said data line driver configured to
responsively provide a write voltage to said write transistor.
Claim 18
Dependent Claim
36 words
The memory circuit as recited in Claim 13 further comprising an address decoder
coupled to said memory array and configured to assert said read signal in response to
receiving an address signal and an enable signal.
Claim 19
Dependent Claim
68 words
The memory circuit as recited in Claim 13 further comprising a bi-directional gate
configured to convert n binary data bits into m logic signals during a write operation,
wherein each of said logic signals has one of said distinct digital values, said bi-directional
gate further configured to convert m logic signals, each having one of said
distinct digital values, into n binary data bits during a read operation.
Claim 20
Dependent Claim
32 words
The memory circuit as recited in Claim 13 further comprising a sense amplifier
coupled to detect said current through said storage transistor, said sense amplifier
configured to responsively provide said input voltage.
References Cited (Backward Citations)
No citation records indexed.
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