Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
372 words
Switching system comprising : a switching structure (1130) for routing cells from a set of M input ports towards a set of M
output ports, said cell comprising a routing header defining to which of said M output ports the
cell is to be routed, a set of distributed individual Switch Core Access Layer elements (S.C.A.L.) (1000), each
distributed SCAL element communicating through one communication link (1400, 1600) to the
input and output port of said switching structure (1130) and allowing attachment to at least one
Protocol Adapter (Protocol Engine 1600- 1900), Each distributed SCAL layer comprising a set of PINT circuits (511-515; 611-614), each PINT
circuit being associated with a corresponding one of said at least Protocol Adapter (Protocol
Engine 1600-1900) and further comprising: a receive part receiving the data cells from the attached Protocol Adapter (Protocol Engine
1600), said receive part including at least one first FIFO storage (701-704) for storing the cells
being received, and introducing at least one extra byte to every cell which will be reserved for a
routing header (bitmap) that will be used by said switching structure for controlling the routing
process within the switching structure; a transmit part comprising at least one second FIFO storage (801-802) having a substantially
greater capacity than said of said first FIFO storage, said transmit part receiving all the cells that
are routed from the associated output port of said switching structure, said transmit part including
means (810) for discarding or not the cells in accordance with the value carried by said at least
one extra byte; Control means for performing Time Division Multiplexing (TDM) access of the at least one first
FIFO and second FIFO to the communication link (1400, 4400) between said distributed
individual SCAL element (1000) and said switching structure. serializing means for performing the conversion of the cells being outputted from said at least first
FIFO into at least one corresponding train of bits that is transmitted through said communication
link (1400); deserializing means for performing the conversion of the flow of bit flows that is received from
the associated output port into a corresponding at least one train ofbytes that can be presented at
the input of said at least one second FIFO (801-804).
Claim 2
Dependent Claim
117 words
Switching system as defined in claim 1 characterized in that said switching structure comprises means for replacing said at least one extra byte introduced by said PINT circuit by a routing
header (bitmap) depending on a routing label (SRH) generated by said Protocol Adapter
(Protocol Engine 1600) comprised into the payload of the cell being routed before said cell is
routed through said switching structure, means for replacing said at least one extra byte by a second routing header depending on the
value of said routing label (SRH) contained in the payloaed of the cell being routed after the
switching of the cell and before said cell is transmitted to the transmit part of said PINT circuit.
Claim 3
Dependent Claim
25 words
Switching system as defined in claim 1 characterized in that said at least one train of bits is
transmitted via at least one coax cable.
Claim 4
Dependent Claim
41 words
Switching system as defined in claim 1 characterized in that said at least one train of bits is
transmitted via an optical coax cable, allowing higher distances between the location of said at
least one SCAL element and said switching structure.
Claim 5
Dependent Claim
196 words
Switching system as defined in claim 1 characterized in that each input port and each output
port can receive and generate four simultaneous bytes, so that said communication link (1400,
1600) is constituted of four parallel flow of bits, each flow corresponding to one of the four bytes
processed by said switching structure, said at least one extra bytes being presented in the data
flow presented in the first of said four flow of bytes; and characterized in that each PINT circuit includes: a receive part that includes four distinctive FIFO storages (701-704), each successively receiving
one byte of the cells coming from said Protocol Adapter (Protocol Engine 1600-1900) and the
first FIFO storage receiving at its first locations said at least extra byte reserved for said routing
header; and a transmit part comprising four distinctive FIFO storages (801-804), each successively receiving
one byte of the cells coming from said associated routed port, means (810) for discarding the cell being received when the value carried by said at least one
extra bytes does not correspond to the particular Protocol Adapter associated to said PINT
circuit, and for suppressing said at least extra byte that were inserted.
Claim 6
Dependent Claim
111 words
Switching system according to claim 5 characterized in that it comprises four individual
switching modules that simultaneously operate the routing process at each input port, said system
further comprising comprising means (1000, 5000) for performing a cell slicing of the cell being
received so that a first switching module receives the first part of the sliced cell with the routing
header, a second switching module receives the second part of the sliced cell, a third switching
module receives the third part of the sliced cell and a fourth switching module receiving the
fburth part of the sliced cell, so that the four different part of the cells are being routed
simultaneously.
Claim 7
Dependent Claim
32 words
Switching system according to claim 6 characterized in that each SCAL element (1000)
communicate with said switching structure by means of four distinctive serialized communication
links using a coax or optical line.