Collar etch method for DRAM cell

Abstract

Abstract In the manufacture of 16 Mbits DRAM chips, a polysilicon strap is used to provide an electrical contact between the drain region of the active NFET device and one electrode of the storage capacitor for each memory cell. In a conventional fabrication process, a Si3N4 pad layer (26) is deposited onto the bare silicon substrate (11) then patterned. Next, deep trenches (17) are formed in the substrate by dry etching. A classic ONO layer (19) is conformally deposited into the trenches. The trenches are filled with undoped polysilicon (18). About 2,5 um of undoped polysilicon are removed from the trench in a plasma etcher. A TEOS SiO2 collar layer (20) is conformally deposited then anisotropically dry etched to leave only the so-called collar. Because trenches are present at the substrate surface, its thickness is not uniform. It is proposed hereunder a novel highly selective dry etch method to anisotropically etch said layer while preserving the Si3N4 pad layer thickness uniformity. According to the present invention, a chemistry having a high TEOS SiO2/Si3N4 selectivity (i.e. which etches TEOS SiO2 faster than Si3N4 by a factor of at least six) is used to etch the TEOS SiO2 collar layer. C4F8/Ar and C4F8/Ar/CO mixtures which have respective selectivities approximately equal to 9:1 and 15:1 (depending on gas ratios) are adequate in all respects. When the surface of the Si3N4 pad layer is reached (this can be accurately detected), the etch is continued by an overetch of the TEOS SiO2 layer to ensure a complete removal of the horizontal portions thereof.

Inventors

• 👤 Philippe Coronel
• 👤 Renzo Maccagnan

Bibliographic Details