Scanning line converting circuit and interpolation coefficient generating circuit

Claim 2

A scanning line converting circuit according to claim 1, wherein said interpolation coefficient generating means generates, when the predetermined scanning line conversion ratio is x:y, ( 1 - K/y ) and (K/y) as respective interpolation coefficients for the chronologically anterior one and the chronologically posterior one of two scanning line signals necessary to generate the post-conversion scanning line signal (where K = (LN×x)%y is satisfied, LN is a number assigned to the post-conversion scanning line signal, and % is remainder calculation).

Claim 3

A scanning line converting circuit according to claim 2, wherein said interpolation coefficient generating means comprises a coefficient control circuit having: a counting portion for incrementing, by x, a number counted thereby with every timing of horizontally synchronizing the post-conversion video signal; and a remainder calculating portion for dividing, by y, the number counted by the counting portion to calculate a remainder, said coefficient control circuit outputting, as said K, a value of the remainder calculated by the remainder calculating portion.

Claim 4

A scanning line converting circuit according to claim 1, wherein said scanning-line selective outputting means has a plurality of line memories for storing the original video signal on a scanning-line basis and is constituted such that respective speeds and timings for signal inputting and signal outputting are independently set and that the scanning line signal necessary to generate the post-conversion scanning line signal is selectively outputted from said plurality of line memories irrespective of relations among the set speeds and timings for signal inputting and signal outputting.

Claim 5

A scanning line converting circuit according to claim 1, further comprising: first delay means for delaying, for a predetermined period, a horizontal synchronizing signal for the original video signal and outputting the delayed signal; and second delay means for delaying, for a predetermined period, a horizontal synchronizing signal for a post-conversion video signal and outputting the delayed signal, said scanning-line selective outputting means being constituted such that respective speeds and timings for signal inputting and signal outputting are independently set, receiving said original video signal on a scanning-line basis at the set speed and with the timing of the output signal from said first delay means, and selectively outputting the scanning line signal necessary to generate the post-conversion scanning line signal at the set speed and with the timing of the output signal from said second delay means.

Claim 6

A scanning line converting circuit for converting the number of signal lines for a video signal, comprising: scanning-line selective outputting means having a plurality of line memories for storing an original video signal on a scanning-line basis, said scanning-line selective outputting means selecting, from scanning line signals stored in the plurality of line memories, at least one necessary to generate a post-conversion scanning line signal and outputting the selected scanning line signal; and scanning line interpolating means for multiplying the scanning line signal selectively outputted from said scanning-line selective outputting means by an interpolation coefficient and adding up the results of multiplication to generate the post-conversion scanning line signal, said scanning-line selective outputting means being constituted such that respective speeds and timings for signal inputting and signal outputting are independently set and that the scanning line signal necessary to generate the post-conversion scanning line signal is selectively outputted from said plurality of line memories irrespective of relations among the set speeds and timings for signal inputting and signal outputting.

Claim 7

A scanning line converting circuit according to claim 6, wherein said plurality of line memories are composed of line memories of a predetermined number obtained by adding N (N is a positive integer) to the number of scanning line signals necessary to generate the post-conversion scanning line signal, each of line memories allowing signal writing and signal reading to be performed independently such that a write operation is performed in accordance with the set speed and timing for signal inputting and that a read operation is performed in accordance with the set speed and timing for signal outputting and said scanning-line selective outputting means comprises: write control means for controlling each of said line memories such that said original video signal is written therein on the scanning-line basis; selecting means for selecting at least one from said plurality of line memories and outputting an output signal from the selected line memory as the signal necessary to generate the post-conversion scanning line signal; and select control means for directing said select means to select the line memory in which the scanning line signal necessary to generate the post-conversion scanning line signal is stored and a read address does not outstrip a write address or a read address is not outstripped by a write address during the read operation performed thereto such that a signal appropriate for the scanning line signal is outputted therefrom.

Claim 8

A scanning line converting circuit according to claim 6, wherein said plurality of line memories are composed of: a first line memory allowing signal writing and signal reading to be performed independently such that said original video signal is written therein on the scanning-line basis in accordance with the set speed and timing for signal inputting and that the scanning line signal is read therefrom in accordance with the set speed and timing for signal outputting; a second line memory receiving an output signal from said first line memory such that signal writing and signal reading is performed in synchronization with a read operation to said first line memory; and an N (N is a positive integer) number of third line memories connected in cascade to said second line memory such that signal writing and signal reading is performed in synchronization with the read operation to said first line memory and said scanning-line selective outputting means is composed of: write control moans for disabling a write operation to said second line memory when a read address outstrips a write address or a read address is outstripped by a write address during the read operation to said first line memory and therefore a signal inappropriate for the scanning line signal is outputted from said first line memory; selecting means for selecting at least one from said plurality of line memories and outputting an output signal from the selected line memory as the scanning line signal necessary to generate the post-conversion scanning line signal; and select control means for directing said selecting means to select the line memory outputting the scanning line signal necessary to generate the post-conversion scanning line signal and not to select said first line memory when a read address outstrips a write address or a read address is outstripped by a write address during the read operation thereto such that a signal inappropriate for the scanning line signal is outputted therefrom.

Claim 9

A scanning line converting circuit according to claim 6, further comprising: first delay means for delaying, for a predetermined period, a horizontal synchronizing signal for the original video signal and outputting the delayed signal; and second delay means for delaying, for a predetermined period, a horizontal synchronizing signal for a post-conversion video signal and outputting the delayed signal, said scanning-line selective outputting means receiving said original video signal on the scanning-line basis at the set speed and with the timing of the output signal from said first delay means and selectively outputting the scanning line signal necessary to generate the post-conversion scanning line signal at the set speed and with the timing of the output signal from said second delay means.

Claim 10

A scanning line converting circuit for converting the number of scanning lines for a video signal and a system for scanning the video signal, comprising: scanning-line selective outputting means for selecting, from scanning line signals composing an original video signal, at least one necessary to generate a post-conversion scanning line signal and outputting the selected scanning line signal; and scanning line interpolating means having interpolation coefficient generating means for generating an interpolation coefficient based on a predetermined scanning line conversion ratio, said scanning line interpolating means multiplying the scanning line signal selectively outputted from said scanning-line selective outputting means by the interpolation coefficient generated from said interpolation coefficient generating means and adding up the results of multiplication to generate the post-conversion scanning line signal, said interpolation coefficient generating means being so constituted as to generate, when the system for scanning the video signal is converted from interlaced scanning to sequential scanning or from sequential scanning to interlaced scanning, an interpolation coefficient in accordance with each field in interlaced scanning such that the post-conversion video signal does not form a blurred image.

Claim 11

A scanning line converting circuit according to claim 10, wherein said interpolation coefficient generating means generates, when the predetermined scanning line conversion ratio is x:y, ( 1 - K/y ) and (K/y) as respective interpolation coefficients for the chronologically anterior one and the chronologically posterior one of two scanning line signals necessary to generate the post-conversion scanning line signal (where K = (LN×x)%y is satisfied, LN is a number assigned to the post-conversion scanning line signal, z is an offset value set in accordance with each field in interlaced scanning, and % is remainder calculation).

Claim 12

A scanning line converting circuit according to claim 11, wherein said interpolation coefficient generating means comprises a coefficient control circuit having: a selecting circuit for selectively outputting, as z, the offset value in accordance with a field under conversion; a counting portion using z selectively outputted from said selecting circuit as a reset value to increment, by x, a number counted thereby with every timing of horizontally synchronizing the post-conversion video signal; and a remainder calculating portion for dividing, by y, the number counted by said counting portion to calculate a remainder, said coefficient control circuit outputting, as said K, a value of the remainder calculated by the remainder calculating portion.

Claim 13

An interpolation coefficient generating circuit used in converting the number of scanning lines for a video signal to generate an interpolation coefficient based on a predetermined ratio for converting the number of scanning lines, said interpolation coefficient generating circuit generating, when the predetermined scanning line conversion ratio is x:y, ( 1 - K/y ) and (K/y) as respective interpolation coefficients for the chronologically anterior one and the chronologically posterior one of two scanning line signals necessary to generate a post-conversion scanning line signal (where K = (LN×x)%y is satisfied, LN is a number assigned to the post-conversion scanning line signal, and % is remainder calculation).

Claim 14

An interpolation coefficient generating circuit according to claim 13, comprising a coefficient control circuit having: a counting portion for incrementing, by x, a number counted thereby with every timing of horizontally synchronizing the post-conversion video signal; and a remainder calculating portion for dividing, by y, the number counted by the counting portion to calculate a remainder, said coefficient control circuit outputting, as said K, a value of the remainder calculated by the remainder calculating portion.

Claim 15

An interpolation coefficient generating circuit used in converting the number of scanning lines for a video signal and a system for scanning the video signal to generate an interpolation coefficient based on a predetermined ratio for converting the number of scanning lines, said interpolation coefficient generating circuit generating, when the scanning line conversion ratio is at x:y, ( 1 - K/y ) and (K/y) as respective interpolation coefficients for the chronologically anterior one and the chronologically posterior one of two scanning line signals necessary to generate a post-conversion scanning line signal (where K = (LN×x)%y is satisfied, LN is a number assigned to the post-conversion scanning line signal, z is an offset value set in accordance with each field in interlaced scanning, and % is remainder calculation).

Claim 16

An interpolation coefficient generating circuit according to claim 15, comprising a coefficient control circuit having: a selecting circuit for selectively outputting, as z, the offset value in accordance with a field under conversion; a counting portion using z selectively outputted from said selecting circuit as a reset value to increment, by x, a number counted thereby with every timing of horizontally synchronizing the post-conversion video signal; and a remainder calculating portion for dividing, by y, the number counted by said counting portion to calculate a remainder, said coefficient control circuit outputting, as said K, a value of the remainder calculated by the remainder calculating portion.