Depuncturing circuit

Claim 1

A depuncturing circuit comprising: write address generator means for generating a write address; first memory means for storing a convolutional code changing its code rate in unit of block at a write address generated by said write address generator means; a counter for counting the number of blocks; second memory means for storing in advance index information representative of a level of an error correction procedure and a corresponding block number and puncturing pattern information to be used a plurality of times corresponding to the block number; read control means for designating a read address through a selective count operation based on the puncturing pattern information and reading data from said first memory means at the designated read address; selector means for selecting either the data read from said first memory means in accordance with the contents of the puncturing pattern information or dummy data if the data read from said first memory means is not selected; puncturing pattern read means for reading the puncturing pattern information from said second memory means by referring to the index information until the block number counted by said counter reaches the block number stored in said second memory means and sending the read puncturing pattern information to said read control means and said selector means; and serial/parallel converter means for converting a serial output of said selector means and the puncturing pattern information into a parallel output and supplying the parallel output to a convolutional code decoder.