Semiconductor device and memory system

Claim 2

A semiconductor memory device according to claim 1, characterized in that said data circuit holds data items to be written into said memory cells.

Claim 3

A semiconductor memory device according to claim 1, characterized in that said data circuit is provided in plurality.

Claim 4

A semiconductor memory device characterized by comprising: a memory cell array having electrically erasable and programmable memory cells arranged in rows and columns, each memory cell capable of storing 2n-value data (n is 1 or a greater natural number) and having a first threshold voltage to store "1," a second threshold voltage higher than the first threshold voltage to store "2," and so forth, and having a 2nth threshold voltage higher than the (2n-1)th threshold voltage to store "2n"; and a data circuit having m latch circuits for holding data items read from said memory cells, wherein during data-reading operation, it is determined whether the threshold voltage of each memory cell is substantially equal to or lower than a voltage corresponding to "n," and whether the threshold voltage of each memory cell is substantially equal to or higher than a voltage corresponding to "n+1," and data items read from said memory cells and held in k latch circuits (k < m) are output from the memory device before data items read from said memory cells are held in the remaining (m-k) latch circuits.

Claim 5

A semiconductor memory device characterized by comprising: a memory cell array having electrically erasable and programmable memory cells arranged in rows and columns, each memory cell capable of storing n-value data (n is 3 or a greater natural number); and t data circuits, each having m latch circuits (m is 2 or a greater natural number) for holding data items to be written into said memory cells and data items read from said memory cells, wherein, of the data items to be written into the memory cells, the first t data items are loaded into the first latch circuits of said data circuits, the next t data items are loaded into the second latch circuits of said data circuits, and so forth, and the last t data items, the first of which is the (i × t + 1)th data item, are loaded into the (i+1)th latch circuits of said data circuits ( 1 ≦ i ≦ m-1 , i is a natural number).

Claim 6

A semiconductor memory device according to claim 5, characterized in that during data-reading operation, a read data item held in the first latch circuit of each data circuit is output before the other m-1 latch circuits hold read data items, a read data item held in the second latch circuit of each data circuit is output before the other (m-2) latch circuits hold read data items, and a read data item held in the j-th latch circuit (1 ≦ j ≦ m; j is a natural number) of each data circuit is output before the other m-j latch circuits hold read data items.

Claim 7

A semiconductor memory device according to claim 5, characterized in that during data-reading operation, a read data item held in the m-th latch circuit of each data circuit is output before the other m-1 latch circuits hold read data items, a read data item held in the (m-1)th latch circuit of each data circuit is output before the other m-2 latch circuits hold read data items, and a read data item held in the p-th latch circuit (1 ≦ p ≦ m; p is a natural number) of each data circuit is output before the other p-1 latch circuits hold read data items.

Claim 8

A semiconductor memory device characterized by comprising: a memory cell array having electrically erasable and programmable memory cells arranged in rows and columns, each memory cell capable of storing n-value data (n is 3 or a greater natural number); and t data circuits, each having m latch circuits (m is 2 or a greater natural number) for holding data items to be written into said memory cells and data items read from said memory cells, wherein, of the data items to be written into the memory cells, the first t data items are loaded into the first latch circuits of said data circuits, the next t data items are loaded into the second latch circuits of said data circuits, and so forth, and the last t data items, the first of which is the (i × t + 1)th data item, are loaded into the (i+1)th latch circuits of said data circuits ( 1 ≦ i ≦ m-1 , i is a natural number); and no write data items are input to f latch circuits of each data circuit (f < m), thereby to program said memory cells, in which f latch circuits hold write data, within the shortest possible time.

Claim 9

A semiconductor memory device according to claim 5, characterized in that during data-reading operation, data items read from said memory cells and held in k latch circuits of each data circuit (k < m) are output before the other m-k latch circuits hold data items read from said memory cells.

Claim 10

A semiconductor memory device according to claim 9, characterized in that during data-reading operation, data items read from said memory cells and held in d latch circuits of each data circuit ( d < m-k ) are output before the other m-k-d latch circuits hold data items read from said memory cells.

Claim 11

A semiconductor memory device characterized by comprising: n-value memory cells (n is 3 or a greater natural number), each having a first threshold voltage to store "1," a second threshold voltage to store "2," a third threshold voltage to store "3," and an i-th threshold voltage to store "i" (i is a natural number equal to or less than n), wherein said memory cells are programmed "1," "2," ..., "k-1," "k," (k > m) according to write data items input from an external device and data items held in said memory cells when said memory cells hold "1," "2," ..., "m-1" and "m" (m is 2 or a greater natural number).

Claim 12

A semiconductor memory device characterized by comprising: n-value memory cells (n is 3 or a greater natural number), each having a first threshold voltage to store "1," a second threshold voltage to store "2," a third threshold voltage to store "3," and an i-th threshold voltage to store "i" (i is a natural number equal to or less than n); programming means for applying a bias to each of said memory cells, thereby to change the threshold voltage of the memory cell over a desired range; and verify means for detecting whether said programming means has changed the threshold voltage of each memory to a desired, every time the bias is applied to the memory cell for a predetermined time, and for causing said programming means to repeatedly applying the bias to the memory cell until the threshold voltage of the memory cell is changed to the desired value, said bias increasing stepwise each time said bias is applied to the memory cell, wherein when each memory cell is programmed to a threshold voltage corresponding to "1," the threshold voltage is changed to a threshold voltage corresponding to "1," "2," ..., "m-1" or "m" (m is 2 or a greater natural number) in a first programming operation according to a write data item input from an external device, and when each memory cell is programmed to a threshold voltage corresponding to "1," "2," ... "m-1," or "m," the threshold voltage is changed to a threshold voltage corresponding to "1," "2," ..., "k-1" or "k" (k is a natural number greater than m) in a second programming operation according to a write data item input from an external device and the threshold voltage of the memory cell; and a step-up value ΔVpp1 by which the bias increases in the first programming operation is less than a step-up value ΔVpp2 by which the bias increases in the second programming operation (ΔVpp1 < ΔVpp2).

Claim 13

A semiconductor memory device according to claim 11 or 12, characterized in that each memory cell stores "1" while assuming an erased state, and the threshold voltage distribution width of "2," "3," ..., "m-1" or "m" in the memory cell is narrower than the threshold voltage distribution width of "m+1," "m+2".

Claim 14

A semiconductor memory device characterized by comprising: n-value memory cells (n is 4 or a greater natural number), each having a first threshold voltage to store "1," a second threshold voltage to store "2," a third threshold voltage to store "3," and an i-th threshold voltage to store "i" (i is a natural number equal to or less than n), wherein when each memory cell holds "1," "2," ..., "2 m-1 -1" or "2 m-1 " (m is a natural number satisfying n = 2 m ), the memory cell comes to store "1," "2," ..., "2 m -1" or "2 m " according to a write data item input from an external device and a data item held in the memory cell.

Claim 15

A semiconductor memory device characterized by comprising: n-value memory cells (n is 4 or a greater natural number), each having a first threshold voltage to store "1," a second threshold voltage to store "2," a third threshold voltage to store "3," and an i-th threshold voltage to store "i" (i is a natural number equal to or less than n); programming means for applying a bias to each of said memory cells, thereby to change the threshold voltage of the memory cell over a desired range; and verify means for detecting whether said programming means has changed the threshold voltage of each memory to a desired value, every time the bias is applied to the memory cell for a predetermined time, and for causing said programming means to repeatedly applying the bias to the memory cell until the threshold voltage of the memory cell is changed to the desired value, said bias increasing stepwise each time said bias is applied to the memory cell, wherein each memory cell has a threshold voltage changed to store "1" or "2" in a first programming operation according to a write data item input from an external device and the threshold voltage of the memory cell when the memory cell has a threshold voltage corresponding to "1", and has a threshold voltage changed to "1," "2," ..., "2 m -1" or "2 m " (m is a natural number satisfying n = 2 m ) in the m-th programming operation according to a write data item input from an external device and the threshold voltage of the memory cell when the memory cell has a threshold voltage corresponding to "1," "2," ..., "2 m-1 -1" or "2 m-1 ,"; and a step-up value ΔVpp1 by which the bias increases in the first programming operation is less than a step-up value ΔVppm by which the bias increases in the m-th programming operation ( ΔVpp1 < ΔVppm).

Claim 16

A semiconductor memory device according to claim 15, characterized in that the threshold voltage distribution width of "2" in the memory cell is narrower than the threshold voltage distribution width of "2 m-1 +1," "2 m-1 +2" ..., "2 m-1 " or "2 m " in the memory cell.

Claim 17

A semiconductor memory device according to claim 14 or 15, characterized in that each memory cell stores "1" while assuming an erased state, and the threshold voltage distribution width of "2," "3," ..., "2 m-1 -1" or "2 m-1 " in the memory cell is narrower than the threshold voltage distribution width of "2 m-1 +1," "2 m-1 +2" ..., "2 m-1 " or "2 m " in the memory cell.

Claim 18

A semiconductor memory device characterized by comprising: n-value memory cells (n is 4 or a greater natural number), each having a first threshold voltage to store "1," a second threshold voltage to store "2," a third threshold voltage to store "3," and an i-th threshold voltage to store "i" (i is a natural number equal to or greater than n), wherein when each memory cell holds "1" or "2," the memory cell comes to store "1," "2," "3," or "4" according to a write data item input from an external device and a data item held in the memory cell.

Claim 19

A semiconductor memory device characterized by comprising: n-value memory cells (n is 3 or a greater natural number), each having a first threshold voltage to store "1," a second threshold voltage to store "2," a third threshold voltage to store "3," and an i-th threshold voltage to store "i" (i is a natural number equal to or less than n); programming means for applying a bias to each of said memory cells, thereby to change the threshold voltage of the memory cell over a desired range; and verify means for detecting whether said programming means has changed the threshold voltage of each memory to a desired value, every time the bias is applied to the memory cell for a predetermined time, and for causing said programming means to repeatedly applying the bias to the memory cell until the threshold voltage of the memory cell is changed to the desired value, said bias increasing stepwise each time said bias is applied to the memory cell, wherein when each memory cell is programmed to a threshold voltage corresponding to "1," the threshold voltage is changed to a threshold voltage corresponding to "1" or "2" in a first programming operation according to a write data item input from an external device; when each memory cell is programmed to a threshold voltage corresponding to "1" or "2," the threshold voltage is changed to a threshold voltage corresponding to "1," "2," "3," or "4" in the second programming operation according to a write data item input from an external device and the threshold voltage of the memory cell; and a step-up value ΔVpp1 by which the bias increases in the first programming operation is less than a step-up value ΔVpp2 by which the bias increases in the second programming operation (ΔVpp1 < ΔVpp2).

Claim 20

A semiconductor memory device according to claim 18, characterized in that each memory cell stores "1" while assuming an erased state, and the threshold voltage distribution width of "2" in the memory cell is narrower than the threshold voltage distribution width of "3" or "4".

Claim 21

A semiconductor memory device characterized by comprising: n-value memory cells (n is 4 or a greater natural number), each having a first threshold voltage to store "1," a second threshold voltage to store "2," a third threshold voltage to store "3," and an i-th threshold voltage to store "i" (i is a natural number equal to or less than n), wherein when each memory cell holds "1," "2," ..., "r-1" or "r" (r is 2 or a greater natural number), the memory cell comes to store "1," "2," ..., "s-1" or "s" (s is a natural number greater than r) according to a write data item input from an external device and a data item held in the memory cell; and when each memory cell holds "1," "2," ..., "s-1" or "s," the memory cell comes to store "1," "2," ..., "t-1" or "t" (t is a natural number greater than s) according to a write data item input from an external device and a data item held in the memory cell.

Claim 22

A semiconductor memory device characterized by comprising: n-value memory cells (n is 4 or a greater natural number), each having a first threshold voltage to store "1," a second threshold voltage to store "2," a third threshold voltage to store "3," and an i-th threshold voltage to store "i" (i is a natural number equal to or less than n); programming means for applying a bias to each of said memory cells, thereby to change the threshold voltage of the memory cell over a desired range; and verify means for detecting whether said programming means has changed the threshold voltage of each memory to a desired value, every time the bias is applied to the memory cell for a predetermined time, and for causing said programming means to repeatedly applying the bias to the memory cell until the threshold voltage of the memory cell is changed to the desired value, said bias increasing stepwise each time said bias is applied to the memory cell, wherein when each memory cell is programmed to a threshold voltage corresponding to "1," 2," ..., "r-1" or "r" (r is 2 or a greater natural number), the threshold voltage is changed to a threshold voltage corresponding to "1," "2," ..., "s-1" or "s" (s is a natural number greater than r) in the j-th programming operation (j is 2 or a greater natural number) according to a write data item input from an external device and threshold voltage of the memory cell; when each memory cell is programmed to a threshold voltage corresponding to "1" or "2," ..., "s-1" or "s," the threshold voltage is changed to a threshold voltage corresponding to "1," "2," ..., "t-1," or "t" (t is a natural number greater than s) in the (j+1)th programming operation according to a write data item input from an external device and the threshold voltage of the memory cell; and a step-up value ΔVppj by which the bias increases in the j-th programming operation is less than a step-up value ΔVpp(j+1) by which the bias increases in the (j+1)th programming operation (ΔVppj < ΔVpp(j+1)).

Claim 23

A semiconductor memory device according to claim 21, characterized in that the threshold voltage distribution width of "r+1," "r+2," ..., "s-1" or "s" in the memory cell is narrower than the threshold voltage distribution width of "s+1," "s+2," ..., "t-1," "t."

Claim 24

A semiconductor memory device according to claim 23, characterized in that each memory cell stores "1" while assuming an erased state, and the threshold voltage distribution width of "2," ..., "r-1" or "r" in the memory cell is narrower than the threshold voltage distribution width of "r+1," "r+2," ..., "s-1," "s."

Claim 25

A semiconductor memory device characterized by comprising: n-value memory cells (n is 4 or a greater natural number), each having a first threshold voltage to store "1," a second threshold voltage to store "2," a third threshold voltage to store "3," and an i-th threshold voltage to store "i" (i is a natural number equal to or less than n), wherein when each memory cell holds "1," "2," ..., "2 k-1 -1" or "2 k-1 " (k is 2 or a greater natural number), the memory cell comes to store "1," "2," ..., "2 k -1" or "2 k " according to a write data item input from an external device and a data item held in the memory cell; and when each memory cell holds "1," "2,"2 k -1" or "2 k ," the memory cell comes to store "1," "2," ..., "2 k+1 -1" or "2 k+1 " according to a write data item input from an external device and a data item held in the memory cell.

Claim 26

A semiconductor memory device characterized by comprising: n-value memory cells (n is 4 or a greater natural number), each having a first threshold voltage to store "1," a second threshold voltage to store "2," a third threshold voltage to store "3," and an i-th threshold voltage to store "i" (i is a natural number equal to or less than n); programming means for applying a bias to each of said memory cells, thereby to change the threshold voltage of the memory cell over a desired range; and verify means for detecting whether said programming means has changed the threshold voltage of each memory to a desired value, every time the bias is applied to the memory cell for a predetermined time, and for causing said programming means to repeatedly applying the bias to the memory cell until the threshold voltage of the memory cell is changed to the desired value, said bias increasing stepwise each time said bias is applied to the memory cell, wherein when each memory cell is programmed to a threshold voltage corresponding to "1," "2," ..., "2 k-1 -1" or "2 k-1 " (k is 2 or a greater natural number), the threshold voltage is changed to a threshold voltage corresponding to "1," "2," ..., "2 k -1" or "2 k " in the k-th programming operation according to a write data item input from an external device and threshold voltage of the memory cell; when each memory cell is programmed to a threshold voltage corresponding to "1" or "2," ..., "2 k -1" or "2 k ," the threshold voltage is changed to a threshold voltage corresponding to "1," "2," ..., "2 k+1 -1," or "2 k+1 " in the (k+1)th programming operation according to a write data item input from an external device and the threshold voltage of the memory cell; and a step-up value ΔVppk by which the bias increases in the kth programming operation is less than a step-up value ΔVpp(k+1) by which the bias increases in the (k+1)th programming operation (ΔVppk < ΔVpp(k+1)).

Claim 27

A semiconductor memory device according to claim 25, characterized in that the threshold voltage distribution width of "2 k-1 +1" or "2 k-1 +2," ..., "2 k -1" and "2 k " in the memory cell is narrower than the threshold voltage distribution width of "2 k +1," "2 k +2," ..., "2 k+1 -1" or "2 k+1 ."

Claim 28

A semiconductor memory device according to claim 25, characterized in that each memory cell stores "1" while assuming an erased state, and the threshold voltage distribution width of "1," "2," ..., "2 k-1 -1" or "2 k-1 " in the memory cell is narrower than the threshold voltage distribution width of "2 k-1 +1," "2 k-1 +2," ..., "2 k -1" or "2 k ."

Claim 29

A semiconductor memory device according to claim 25, characterized in that each memory cell stores "1" while assuming an erased state, and the threshold voltage distribution width of "2" in the memory cell is narrower than the threshold voltage distribution width of "3," "4," ..., "2 k-1 -1" or "2 k-1 ."

Claim 30

A semiconductor memory device characterized by comprising: n-value memory cells (n is 3 or a greater natural number), each having a first threshold voltage to store "1," a second threshold voltage to store "2," a third threshold voltage to store "3," and an i-th threshold voltage to store "i" (i is a natural number equal to or less than n), wherein during the first programming operation, each memory cell stores "1" in the input data is a first logic level and stores "2" in the input data is a second logic level, and during the kth programming operation, each memory cell stores "A" in the input data is a (2k-1)th logic level and stores "A+2 k-1 " in the input data is a 2kth logic level in the case where the memory cell has been storing "A" during a (k-1)th programming operation (k is 2 or a greater natural number).

Claim 31

A semiconductor memory device characterized by comprising: n-value memory cells (n is 3 or a greater natural number), each having a first threshold voltage to store "1," a second threshold voltage to store "2," a third threshold voltage to store "3," and an i-th threshold voltage to store "i" (i is a natural number equal to or less than n); programming means for applying a bias to each of said memory cells, thereby to change the threshold voltage of the memory cell over a desired range; and verify means for detecting whether said programming means has changed the threshold voltage of each memory to a desired value, every time the bias is applied to the memory cell for a predetermined time, and for causing said programming means to repeatedly applying the bias to the memory cell until the threshold voltage of the memory cell is changed to the desired value, said bias increasing stepwise each time said bias is applied to the memory cell, wherein during the first programming operation, each memory cell stores "1" in the input data is a first logic level and stores "2" in the input data is a second logic level, and during the kth programming operation, each memory cell stores "A" in the input data is a (2k-1)th logic level and stores "A+2 k-1 " in the input data is a 2kth logic level in the case where the memory cell has been storing "A" during a (k-1)th programming operation (k is 2 or a greater natural number); and a step-up value ΔVpp1 by which the bias increases in the first mode for performing the first programming operation is less than a step-up value ΔVppk by which the bias increases in the kth programming operation for performing the k-th programming operation (ΔVpp1 < ΔVppk).

Claim 32

A semiconductor memory device according to claim 30 or 31, characterized in that each memory cell stores "1" while assuming an erased state, and the threshold voltage distribution width of "2" in the memory cell is narrower than the threshold voltage distribution width of "A+2 k-1 ."

Claim 33

A semiconductor memory device according to claim 30 or 31, characterized in that the threshold voltage distribution width of "A" in the memory cell is narrower than the threshold voltage distribution width of "A+2 k-1 ."

Claim 34

A semiconductor memory device characterized by comprising: n-value memory cells (n is 4 or a greater natural number), each having a first threshold voltage to store "1," a second threshold voltage to store "2," a third threshold voltage to store "3," and an i-th threshold voltage to store "i" (i is a natural number equal to or less than n), wherein during the first programming operation, each memory cell stores "1" in the input data is a first logic level and stores "2" in the input data is a second logic level; during the second programming operation, each memory cell stores "1" in the input data is a third logic level or stores "3" in the input data is a fourth logic level in the case where the memory cell has been storing "1" during the first programming operation; and during the second programming operation, each memory cell stores "2" in the input data is the third logic level or stores "4" in the input data is the fourth logic level in the case where the memory cell has been storing "2" during the first programming operation.

Claim 35

A semiconductor memory device characterized by comprising: n-value memory cells (n is 4 or a greater natural number), each having a first threshold voltage to store "1," a second threshold voltage to store "2," a third threshold voltage to store "3," and an i-th threshold voltage to store "i" (i is a natural number equal to or less than n); programming means for applying a bias to each of said memory cells, thereby to change the threshold voltage of the memory cell over a desired range; and verify means for detecting whether said programming means has changed the threshold voltage of each memory to a desired value, every time the bias is applied to the memory cell for a predetermined time, and for causing said programming means to repeatedly applying the bias to the memory cell until the threshold voltage of the memory cell is changed to the desired value, said bias increasing stepwise each time said bias is applied to the memory cell, wherein during the first programming operation, each memory cell stores "1" in the input data is a first logic level and stores "2" in the input data is a second logic level; during the second programming operation, each memory cell stores "1" in the input data is a third logic level or stores "3" in the input data is a fourth logic level in the case where the memory cell has been storing "1" during the first programming operation; during the second programming operation, each memory cell stores "2" in the input data is the third logic level or stores "4" in the input data is the fourth logic level in the case where the memory cell has been storing "2" during the first programming operation; and a step-up value ΔVpp1 by which the bias increases in the first mode for performing the first programming operation is less than a step-up value ΔVpp2 by which the bias increases in the second programming operation for performing the second programming operation (ΔVpp1 < ΔVpp2).

Claim 36

A semiconductor memory device according to claim 34, characterized in that each memory cell stores "1" while assuming an erased state, and the threshold voltage distribution width of "2" in the memory cell is narrower than the threshold voltage distribution width of "3" or "4."

Claim 37

A semiconductor memory device according to claim 34, characterized in that the third threshold voltage is higher than the second threshold voltage.

Claim 38

A semiconductor memory device according to claim 37, characterized in that a difference between threshold voltage distributions corresponding to "3" and "4" is equal to a difference between threshold voltage distributions corresponding to "2" and "3."

Claim 39

A semiconductor memory device according to claim 37, characterized in that a difference between threshold voltage distributions corresponding to "3" and "4" is greater than a difference between threshold voltage distributions corresponding to "2" and "3."

Claim 40

A semiconductor memory device according to claim 34, characterized in that the third threshold voltage is lower than the second threshold voltage.

Claim 41

A semiconductor memory device according to claim 40, characterized in that a difference between threshold voltage distributions corresponding to "2" and "4" is equal to a difference between threshold voltage distributions corresponding to "2" and "3."

Claim 42

A semiconductor memory device according to claim 40, characterized in that a difference between threshold voltage distributions corresponding to "2" and "4" is greater than a difference between threshold voltage distributions corresponding to "2" and "3."

Claim 43

A semiconductor memory device characterized by comprising: n-value memory cells (n is 4 or a greater natural number), each having a first threshold voltage to store "1," a second threshold voltage to store "2," a third threshold voltage to store "3," and an i-th threshold voltage to store "i" (i is a natural number equal to or less than n), wherein during the first programming operation, each memory cell stores "1" in the input data is a first logic level and stores "2" in the input data is a second logic level; during the second programming operation, each memory cell stores "1" in the input data is a third logic level and according to the data item held in the memory cell, and stores "3" in the input data is a fourth logic level and according to the data item held in the memory cell, in the case where the memory cell has been storing "1" during the first programming operation; and during the second programming operation, each memory cell stores "2" in the input data is the third logic level and the data item held in the memory cell, and stores "4" in the input data is the fourth logic level and the data item held in the memory cell, in the case where the memory cell has been storing "2" during the first programming operation.

Claim 44

A semiconductor memory device characterized by comprising: n-value memory cells (n is 4 or a greater natural number), each having a first threshold voltage to store "1," a second threshold voltage to store "2," a third threshold voltage to store "3," and an i-th threshold voltage to store "i" (i is a natural number equal to or less than n); and a data circuit for holding a write data to be written into said memory cells, wherein each memory cell stores "1" when a first write data item held in said data circuit is at a first logic level and stores "2" when the first write data item is at a second logic level; and after said data circuit holds a second write data item input from an external device and a data item read from each memory cell, the memory comes to store "1" when the memory cell stores "1" and said data circuit holds the second write data item of a third logic level, comes to store "3" when the memory cell stores "1" and said data circuit holds the second write data item of a fourth logic level, comes to store "2" when the memory cell stores "2" and said data circuit holds the second write data item of the third logic level, comes to store "4" when the memory cell stores "2" and said data circuit holds the second write data item of the fourth logic level.

Claim 45

A semiconductor memory device according to claim 34, characterized in that the first logic level is equal to the third logic level, and the second logic level is equal to the fourth logic level.

Claim 46

A semiconductor memory device according to claim 35, characterized in that the first logic level is equal to the third logic level, and the second logic level is equal to the fourth logic level.

Claim 47

A semiconductor memory device according to claim 43, characterized in that the first logic level is equal to the third logic level, and the second logic level is equal to the fourth logic level.

Claim 48

A semiconductor memory device according to claim 44, characterized in that the first logic level is equal to the third logic level, and the second logic level is equal to the fourth logic level.

Claim 49

A semiconductor memory device characterized by comprising: n-value memory cells (n is 3 or a greater natural number), each having a first threshold voltage to store "1," a second threshold voltage to store "2," a third threshold voltage to store "3," and an i-th threshold voltage to store "i" (i is a natural number equal to or less than n); and a data circuit for holding a write data to be written into said memory cells, wherein when each memory cell stores "1," "2," ..., "m-1," "m" ( m is a natural number greater than 2), the memory cell stores "1," "2," ..., "k-1" or "k" (k is a natural number greater than m) according to a write data item input from an external device and also a data item read from the memory cell and held in the data circuit.

Claim 50

A semiconductor memory device characterized by comprising: n-value memory cells (n is 3 or a greater natural number), each having a first threshold voltage to store "1," a second threshold voltage to store "2," a third threshold voltage to store "3," and an i-th threshold voltage to store "i" (i is a natural number equal to or less than n); and a data circuit for holding a write data to be written into said memory cells, programming means for applying a bias to each of said memory cells, thereby to change the threshold voltage of the memory cell over a desired range; and verify means for detecting whether said programming means has changed the threshold voltage of each memory to a desired value, every time the bias is applied to the memory cell for a predetermined time, and for causing said programming means to repeatedly applying the bias to the memory cell until the threshold voltage of the memory cell is changed to the desired value, said bias increasing stepwise each time said bias is applied to the memory cell, wherein when each memory cell is at a threshold voltage to store "1," the memory cell is programmed to a threshold voltage to store "1," "2," ..., "m-1" or "m" (m is 2 or a greater natural number) in a first programming operation according to a write data item input from an external device and held in the data circuit; when each memory cell is at a threshold voltage to store "1," "2," ..., "m-1" or "m," the memory cell is programmed to a threshold voltage to store "1," "2," ..., "k-1" or "k" (k is a natural number greater than m) in a second programming operation according to a write data input from the external device and held in the data circuit and also a data item read from the memory cell; and a step-up value ΔVpp1 by which the bias increases in the first programming operation is less than a step-up value ΔVpp2 by which the bias increases in the second programming operation (ΔVpp1 < ΔVpp2).

Claim 51

A semiconductor memory device- according to claim 49, characterized in that each memory cell stores "1" while assuming an erased state, and the threshold voltage distribution width of "2," "3,", ..., "m-1" or "m" in the memory cell is narrower than the threshold voltage distribution width of "m+1," "m+2," ..., "k-1" or "k."

Claim 52

A semiconductor memory device characterized by comprising: n-value memory cells (n is 3 or a greater natural number), each having a first threshold voltage to store "1," a second threshold voltage to store "2," a third threshold voltage to store "3," and an i-th threshold voltage to store "i" (i is a natural number equal to or less than n); and a data circuit for holding a write data to be written into said memory cells, wherein when each memory cell stores "1" or "2," the memory cell is programmed to "1," "2," "3" or "4" according to a write data item input from an external device and also a data item read from the memory cell and held in the data circuit.

Claim 53

A semiconductor memory device characterized by comprising: n-value memory cells (n is 4 or a greater natural number), each having a first threshold voltage to store "1," a second threshold voltage to store "2," a third threshold voltage to store "3," and an i-th threshold voltage to store "i" (i is a natural number equal to or less than n); and a data circuit for holding a write data to be written into said memory cells, programming means for applying a bias to each of said memory cells, thereby to change the threshold voltage of the memory cell over a desired range; and verify means for detecting whether said programming means has changed the threshold voltage of each memory to a desired value, every time the bias is applied to the memory cell for a predetermined time, and for causing said programming means to repeatedly applying the bias to the memory cell until the threshold voltage of the memory cell is changed to the desired value, said bias increasing stepwise each time said bias is applied to the memory cell, wherein when each memory cell is at a threshold voltage to store "1," the memory cell is programmed to a threshold voltage to store "1" or "3" in a first programming operation according to a write data item input from an external device and held in the data circuit; when each memory cell is at a threshold voltage to store "1" or "2," the memory cell is programmed to a threshold voltage to store "1," "2," "3" or "4" in a second programming operation according to a write data input from the external device and also a data item read from the memory cell and held in the data circuit; and a step-up value ΔVpp1 by which the bias increases in the first programming operation is less than a step-up value ΔVpp2 by which the bias increases in the second programming operation (ΔVpp1 < ΔVpp2).

Claim 54

A semiconductor memory device according to claim 52, characterized in that each memory cell stores "1" while assuming an erased state, and the threshold voltage distribution width of "2" in the memory cell is narrower than the threshold voltage distribution width of "3" or "4."

Claim 55

A semiconductor memory device characterized by comprising: memory cells capable of storing multi-bit data items; and a data circuit for holding an data item to be written into said memory cells, wherein each of said multi-bit data item contains upper bit and lower bit; the upper bit is written into each memory cell after a first write data item is input from an external device and temporarily held in said data circuit; and the lower bit is written into the memory cell after a second write data item is input from the external device and temporarily held in said data circuit.

Claim 56

A semiconductor memory device according to claim 55, characterized in that the lower bit is written in each memory cell after the second write data item input from the external device and the upper bit read from the memory cell is held in said data circuit.

Claim 57

A semiconductor memory device characterized by comprising: a plurality of memory cells, each capable of storing multi-bit data item, said memory cells divided into a plurality of groups, each containing a predetermined number of memory cells and constituting a page; a data circuit for holding data items to be written into said memory cells, wherein each of said multi-bit data item contains upper bit to be written first into each memory cell and lower bit to be written next into each memory cell, the upper bit is first written into the memory cells of one group constituting an upper page, and the lower bits are then written into the memory cells of another group constituting a lower page.

Claim 58

A semiconductor memory device according to claim 57, characterized in that said upper page is written after a first data item is input to said data circuit from an external device and temporarily held in said data circuit, and said lower page is then written after a second data item is input to said data circuit from the external device temporarily held in said data circuit.

Claim 59

A semiconductor memory device according to claim 57, characterized in that said memory cells are divided into groups, and said data circuit is provided in plurality, each provided for one group of memory cells.

Claim 60

A semiconductor memory device characterized by comprising: memory cells capable of storing multi-bit data items; a data circuit for holding a write data item to be written into said memory cells; programming means for programming said memory cells according to the write data item held in said data circuit; and verify means for detecting whether said programming means has written the write data item held in said data circuit, into said memory cells, and for causing said programming means to repeatedly applying the bias to the memory cell until said programming means sufficiently programs said memory cells, wherein each of said multi-bit data item contains upper bit and lower bit; said programming means writes said upper bit into each memory cell after said verify means detects that said programming means has sufficiently programmed and said programming means writes said lower bits into the memory cell .

Claim 61

A semiconductor memory device according to claim 60, characterized in that said lower bit is written into the memory cell after said upper bit has been written into the memory cell and after said data circuit holds a write data item input from an external device and the upper bits read from the memory cell.

Claim 62

A semiconductor memory device characterized by comprising: a plurality of memory cells, each capable of storing multi-bit data item, said memory cells divided into a plurality of groups, each containing a predetermined number of memory cells and constituting a page; a data circuit for holding data items to be written into said memory cells, programming means for programming said memory cells according to the write data item held in said data circuit; and verify means for detecting whether said programming means has written the write data item held in said data circuit, into said memory cells, and for causing said programming means to repeatedly applying the bias to the memory cell until said programming means sufficiently programs said memory cells, wherein each of said multi-bit data item contains upper bit and lower bit, said programming means writes the upper bit into the memory cells of a group constituting an upper page after said verify means detects that said programming means has sufficiently programmed the memory cell of the group constituting the upper page, and said programming means writes the lower bits into the memory cells of another group constituting a lower page.

Claim 63

A semiconductor memory device according to claim 62, characterized in that said lower bit is written into the memory cell after said upper bit has been written into the memory cell and after said data circuit holds a write data item input from an external device and the upper bit read from the memory cell.

Claim 64

A semiconductor memory device according to claim 62, characterized in that said data circuit is provided in plurality, each provided for one group of memory cells.

Claim 65

A semiconductor memory device characterized by comprising: n-value memory cells (n is 3 or a greater natural number), each capable of storing multi-bit data item, a page block containing said memory cells; wherein a memory cell of a first page block is programmed in the p-th programming operation (p is 1 or a greater natural number), and a memory cell of a first page block is programmed in the (p+1)th programming operation after the first and the second page blocks have been programmed in the p-th programming operation.

Claim 66

A semiconductor memory device characterized by comprising: a plurality of memory cells, each capable of storing multi-bit data item, a page block containing memory cells; a data circuit for holding data items to be written into said memory cells, programming means for programming said memory cells according to the write data item held in said data circuit; and verify means for detecting whether said programming means has written the write data item held in said data circuit, into said memory cells, and for causing said programming means to repeatedly applying the bias to the memory cell until said programming means sufficiently programs said memory cells, wherein a memory cell of a first page block is programmed in the p-th programming operation (p is 1 or a greater natural number), and a memory cell of a first page block is programmed in the (p+1)th programming operation after the first page and the second page blocks have been programmed in the p-th programming operation.

Claim 67

A semiconductor memory device according to claim 65 or 66, characterized in that the (p+1)th programming operation is performed on the second page after the (p+1)th programming operation has been performed on the first page.

Claim 68

A semiconductor memory device according to claim 66, characterized in that said programming means performs the p-th programming operation on the second memory after said verify means detects that the first memory is sufficiently programmed in the p-th programming operation.

Claim 69

A semiconductor memory device according to claim 66, characterized in that said programming means performs the (p+1)th programming operation on the first memory after said verify means detects that the second memory is sufficiently programmed in the p-th programming operation.

Claim 70

A semiconductor memory device according to claim 65 or 66, characterized in that the p-th programming operation is first programming operation, and the (p+1)th programming operation is the second programming operation.

Claim 71

A semiconductor memory device according to claim 70, characterized in that each of said memory cells is an n-value memory cell (n is 3 or a greater natural number) which has a first threshold voltage to store "1," a second threshold voltage to store "2," a third threshold voltage to store "3," and an i-th threshold voltage to store "i" (i is a natural number equal to or less than n); when each memory cell is at a threshold voltage to store "1," said first programming operation is performed in a first programming operation according to a write data item input from an external device, thereby to set the memory cell at a threshold voltage to store "1," "2," ..., "m-1" or "m" (m is 2 or a greater natural number); when each memory cell is at a threshold voltage to store "1," "2," ..., "m-1" or "m," said second programming operation is performed in a second programming operation according to a write data item input from the external device and also the threshold voltage of the memory cell, thereby to the memory cell at a threshold voltage to store "1," "2," ..., "k-1," "k," (k > m).

Claim 72

A semiconductor memory device according to claim 65 or 66, characterized in that each of said memory cells is an n-value memory cell (n is 4 or a greater natural number) which has a first threshold voltage to store "1," a second threshold voltage to store "2," a third threshold voltage to store "3," and an i-th threshold voltage to store "i" (i is a natural number equal to or less than n); when each memory cell is at a threshold voltage to store "1," "2,", ..., "r-1" or "r" (r is 2 or a greater natural number), said p-th programming operation is performed in a j-th programming operation (j is 2 or a greater natural number) according to a write data item input from an external device and also the threshold voltage of the memory cell, thereby to set the memory cell at a threshold voltage to store "1," "2," ..., "s-1" or "s" (s is a natural number greater than r); when each memory cell is at a threshold voltage to store "1," "2," ..., "s-1" or "s," said (p+1)th programming operation is performed in a (j+1)th programming operation according to a write data item input from the external device and also the threshold voltage of the memory cell, thereby to set the memory cell at a threshold voltage to store "1," "2," ..., "t-1" or "t" (t is a natural number greater than s).

Claim 73

A semiconductor memory device characterized by comprising: n-value memory cells (n is 3 or a greater natural number), each capable of storing multi-bit data item, a page block containing memory cells; wherein the (p+1)th programming operation (p is 1 or a greater natural number) is performed on the memory cells constituting the first page block after the p-th programming operation has been performed on the memory cells constituting the first page block and after the p-th programming operation has been performed on the memory cells constituting the second page block.

Claim 74

A semiconductor memory device characterized by comprising: a plurality of memory cells, each capable of storing multi-bit data item, said memory cells divided into a plurality of groups, a page block containing memory cells; a data circuit for holding data items to be written into said memory cells, programming means for programming said memory cells according to the write data item held in said data circuit; and verify means for detecting whether said programming means has written the write data item held in said data circuit, into said memory cells, and for causing said programming means to repeatedly applying the bias to the memory cell until said programming means sufficiently programs said memory cells, wherein the (p+1)th programming operation (p is 1 or a greater natural number) is performed on the memory cells constituting the first page block after the p-th programming operation has been performed on the memory cells constituting the first page block and after the p-th programming operation has been performed on the memory cells constituting the second page block.

Claim 75

A semiconductor memory device according to claim 73 or 74, characterized in that said (p+1)th programming operation is performed on the memory cells constituting the second page block after said (p+1)th programming operation has been performed on the memory cells constituting the first page block.

Claim 76

A semiconductor memory device according to claim 74, characterized in that said programming means performs the p-th programming operation on the memory cells constituting the second page block after said verify means detects that all memory cells constituting the first page block are sufficiently programmed in the p-th programming operation.

Claim 77

A semiconductor memory device according to claim 74, characterized in that said programming means performs the (p+1)th programming operation on the memory cells constituting the first page block after said verify means detects that all memory cells constituting the second page block are sufficiently programmed in the p-th programming operation.

Claim 78

A semiconductor memory device according to claim 73 or 74, characterized in that the p-th programming operation is the first programming operation, and the (p+1)th programming operation is the second programming operation.

Claim 79

A semiconductor memory device according to claim 78, characterized in that each of said memory cells is an n-value memory cell (n is 3 or a greater natural number) which has a first threshold voltage to store "1," a second threshold voltage to store "2," a third threshold voltage to store "3," and an i-th threshold voltage to store "i" (i is a natural number equal to or less than n); when each memory cell is at a threshold voltage to store "1," said first programming operation is performed in a first programming operation according to a write data item input from an external device, thereby to set the memory cell at a threshold voltage to store "1," "2," ..., "m-1" or "m" (m is 2 or a greater natural number); when each memory cell is at a threshold voltage to store "1," "2," ..., "m-1" or "m," said second programming operation is performed in a second programming operation according to a write data item input from the external device and also the threshold voltage of the memory cell, thereby to the memory cell at a threshold voltage to store "1," "2," ..., "k-1," "k" (k > m).

Claim 80

A semiconductor memory device according to claim 73 or 74, characterized in that each of said memory cells is an n-value memory cell (n is 4 or a greater natural number) which has a first threshold voltage to store "1," a second threshold voltage to store "2," a third threshold voltage to store "3," and an i-th threshold voltage to store "i" (i is a natural number equal to or less than n); when each memory cell is at a threshold voltage to store "1," "2,", ..., "r-1" or "r" (r is 2 or a greater natural number), said p-th programming operation is performed in a j-th programming operation (j is 2 or a greater natural number) according to a write data item input from an external device and also the threshold voltage of the memory cell, thereby to set the memory cell at a threshold voltage to store "1," "2," ..., "s-1" or "s" (s is a natural number greater than r); when each memory cell is at a threshold voltage to store "1," "2," ..., "s-1" or "s," said (p+1)th programming operation is performed in a (j+1)th programming operation according to a write data item input from the external device and also the threshold voltage of the memory cell, thereby to set the memory cell at a threshold voltage to store "1," "2," ..., "t-1" or "t" (t is a natural number greater than s).

Claim 81

A semiconductor memory device according to claim 73 or 74, characterized in that the (p+1)th programming operation is performed on the memory cells constituting the first page block after the p-th programming operation has been performed on all the memory cells provided in the device.

Claim 82

A semiconductor memory device according to claim 65, 69, 73 or 74, characterized in that the number of times said (p+1)th programming operation has been performed on each page block is recorded, and the order in which the page blocks are to be programmed is determined according to the number of times recorded.

Claim 83

A memory system characterized by comprising: a plurality of semiconductor memory devices, each having memory cells capable of storing multi-bit data item, said memory cells divided into a plurality of groups, each containing a predetermined number of memory cells and constituting a page; wherein the (p+1)th programming operation (p is 1 or a greater natural number) is performed on the memory cells provided on a first semiconductor memory device after the p-th programming operation has been performed on the memory cells provided in the first semiconductor memory device and after the p-th programming operation has been performed on the memory cells provided in the second semiconductor memory device.

Claim 84

A semiconductor memory device according to claim 83, characterized in that the (p+1)th programming operation is performed on the memory cells provided in the second semiconductor memory device after the (p+1)th programming operation is performed on the memory cells provided in the first semiconductor memory device.

Claim 85

A memory system according to claim 84, characterized in that the (p+1)th programming operation is performed on the memory cells provided in the second semiconductor memory device after the (p+1)th programming operation is performed on only a part of the memory cells provided in the first semiconductor memory device.

Claim 86

A memory system according to claim 83, characterized in that the p-th programming operation is the first programming operation, and the (p+1)th programming operation is the second programming operation.

Claim 87

A memory system according to claim 86, characterized in that each of said memory cells is an n-value memory cell (n is 3 or a greater natural number) which has a first threshold voltage to store "1," a second threshold voltage to store "2," a third threshold voltage to store "3," and an i-th threshold voltage to store "i" (i is a natural number equal to or less than n); when each memory cell is at a threshold voltage to store "1," said first programming operation is performed in a first programming operation according to a write data item input from an external device, thereby to set the memory cell at a threshold voltage to store "1," "2," ..., "m-1" or "m" (m is 2 or a greater natural number); when each memory cell is at a threshold voltage to store "1," "2," ..., "m-1" or "m," said second programming operation is performed in a second programming operation according to a write data item input from the external device and also the threshold voltage of the memory cell, thereby to the memory cell at a threshold voltage to store "1," "2," ..., "k-1," "k" (k > m).

Claim 88

A memory system according to claim 83, characterized in that each of said memory cells is an n-value memory cell (n is 4 or a greater natural number) which has a first threshold voltage to store "1," a second threshold voltage to store "2," a third threshold voltage to store "3," and an i-th threshold voltage to store "i" (i is a natural number equal to or less than n); when each memory cell is at a threshold voltage to store "1," "2,", ..., "r-1" or "r" (r is 2 or a greater natural number), said p-th programming operation is performed in a j-th programming operation (j is 2 or a greater natural number) according to a write data item input from an external device and also the threshold voltage of the memory cell, thereby to set the memory cell at a threshold voltage to store "1," "2," ..., "s-1" or "s" (s is a natural number greater than r); when each memory cell is at a threshold voltage to store "1," "2," ..., "s-1" or "s," said (p+1)th programming operation is performed in a (j+1)th programming operation according to a write data item input from the external device and also the threshold voltage of the memory cell, thereby to set the memory cell at a threshold voltage to store "1," "2," ..., "t-1" or "t" (t is a natural number greater than s).

Claim 89

A memory system according to claim 83, characterized in that the (p+1)th programming operation is performed on the memory cells provided in the first semiconductor device after the p-th programming operation has been performed on all the memory cells provided in all semiconductor devices.

Claim 90

A memory system according to claim 83, characterized by further comprising control means for controlling said semiconductor memory devices.

Claim 91

A memory system according to claim 90, characterized in that said control means controls the order in which memory cells are programmed.

Claim 92

A memory system according to claim 91, characterized in that said order is determined in units of memory cells that share the same word line.

Claim 93

A memory system according to claim 91, characterized in that said order is determined in units of semiconductor memory devices.