EP0794525A2
Expired / Lapsed
EP
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Pixel conversion apparatus
Assignee: Panasonic Holdings Corp
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Filing: 1997-03-03
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Granted: —
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Expires: 2017-03-03
Abstract
Abstract A pixel conversion apparatus of the present invention includes sync separation means for separating a sync signal from an input signal, pixel conversion information analysis means for analyzing how to convert the number of pixels to display the input signal as an image from the input signal and a picture display area, timing signal generation means for generating a timing signal for displaying an image according to the outputs of the sync separation means and the pixel conversion information analysis means, pixel conversion means for processing a pixel conversion of the input signal according to the output of the timing signal generation means, interpolation means for processing a pixel interpolation when pixel to be interpolated generates by pixel conversion at the pixel conversion means, and sync signal generation means for generating a sync signal for displaying the input signal as an image. Because the relation between the input signal and the image display area is previously analyzed and processed, there is no lack or display by mistake of image information included in the input signal and a high quality image can be effectively displayed on the picture display area of the display device.
Inventors
- 👤 Takahisa Hatano
- 👤 Taro Funamoto
- 👤 Fumiou Kameoka
- 👤 Yoshikuni Shindo
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 13:29
CPC Classifications
G; G09; G09G; G09G5/00; G09G5/003; G09G5/005; G09G3/00; G09G3/20; G09G3/34; G09G3/36; G09G3/3611; H; H04; H04N; H04N7/00; H04N7/01; H04N7/0135; G09G2340/00; G09G2340/04; G09G2340/0407; G09G2340/0414; G09G2340/0421; G09G2340/0442; G09G5/006; G09G5/18
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
140 words
A pixel conversion apparatus comprising: sync separation means for separating sync signals from an input video signal; pixel conversion information analysis means for analyzing how the number of pixels is to be converted for displaying said input video signal from said input video signal and a picture display area; timing generation means for generating a timing signal for displaying a picture according to the outputs of said sync separation means and said pixel conversion information analysis means; pixel conversion means for converting the number of pixels of said input video signal according to the output of said timing generation means; interpolation means for interpolating the pixels by the pixel conversion at said pixel conversion means when some pixels must be interpolated; and sync signal generation means for generating a sync signal for displaying said input video signal as a picture.
Claim 2
Dependent Claim
79 words
A pixel conversion apparatus as recited in claim 1, wherein: said pixel conversion information analysis means discriminates the number of pixels and the effective area of said input video signal and calculates the blanking period of the picture displaying said input video signal from the discriminated result and the picture display area and the timing of the horizontal sync signal from said sync signal generation means is different between at said effective picture area and at said blanking period.
Claim 3
Dependent Claim
55 words
A pixel conversion apparatus as recited in claim 1, wherein: said pixel conversion information analysis means discriminates interlace or non-interlace of said input video signal and discriminates odd field or even field of said interlaced signal and said interpolation means processes a different interpolation between odd field and even field according to the discrimination result.
Claim 4
Dependent Claim
45 words
A pixel conversion apparatus as recited in claim 1, wherein: said pixel conversion information analysis means calculates a plurality of clocks necessary for pixel conversion and said timing signal generation means gives a designated modulation to at least one clock of said plurality of clocks.
Claim 5
Dependent Claim
44 words
A pixel conversion apparatus as recited in claim 1, wherein: said pixel conversion information analysis means calculates a pixel conversion ratio and comprises control means for controlling writing to a memory of the pixels interpolated at said interpolation means according to said calculation result.
Claim 6
Dependent Claim
37 words
A pixel conversion apparatus wherein the horizontal sync signal timing is made different from at the effective picture area and at the blanking period when the number of scanning lines of an input video signal is converted.
Claim 7
Dependent Claim
121 words
A pixel conversion apparatus comprising: sync separation circuit for separating a horizontal sync signal and a vertical sync signal from an input video signal; first PLL circuit for generating a first clock signal synchronizing with the separated horizontal sync signal outputted from said sync separation circuit; second PLL circuit for generating a second clock signal synchronizing with said separated horizontal sync signal; scanning line conversion circuit for converting the number of scanning lines of said input video signal; and timing signal generation circuit for generating an interpolation timing signal and an interpolation coefficient for horizontal and vertical interpolation at said scanning line conversion circuit and generating a horizontal sync signal having a plurality of horizontal scanning frequency after scanning line conversion.
Claim 8
Dependent Claim
77 words
A pixel conversion apparatus converting the frame frequency using a clock frequency which the integer times of the number of clocks n before scanning line conversion is the integer times of the number of clocks m after scanning line conversion at scanning line conversion of an input video signal, where m is the total number of clocks per frame before scanning line conversion and n is the total number of clocks per frame after scanning line conversion.
Claim 9
Dependent Claim
142 words
A pixel conversion apparatus comprising: a sync separation circuit for separating a horizontal sync signal and a vertical sync signal from an input video signal; a first PLL circuit for generating a first clock signal synchronizing with the separated horizontal sync signal outputted from said sync separation circuit; a second PLL circuit for generating a second clock signal synchronizing with said separated horizontal sync signal; a scanning line conversion circuit for converting the number of scanning lines of said input video signal; a timing signal generation circuit for generating an interpolation timing signal and an interpolation coefficient for horizontal and vertical interpolation at said scanning line conversion circuit and generating a horizontal sync signal having a plurality of horizontal scanning frequency after scanning line conversion; and a memory for converting the frame frequency of the output of said scanning line conversion circuit.
Claim 10
Dependent Claim
43 words
A pixel conversion apparatus in which interlace or non-interlace and odd field or even field are discriminated for an input video signal and when the input video signal is interlaced, a different interpolation is processed between for odd field and for even field.
Claim 11
Dependent Claim
47 words
A pixel conversion apparatus featuring that an interpolation timing circuit for vertical interpolation is reset at every frame when the input video signal is non-interlaced and a sync signal generation circuit for various kinds of pulses necessary for a driving display circuit is reset at every field.
Claim 12
Dependent Claim
144 words
A pixel conversion apparatus comprising: a sync separation circuit for separating a horizontal sync signal and a vertical sync signal from an input video signal; a field discrimination circuit for discriminating a field parity of said input video signal; a scanning line conversion circuit for converting the number of scanning lines of said input video signal; a first delay device for delaying the output of said scanning line conversion circuit by one horizontal period; a second delay device for delaying the output of said delay device by one horizontal period; a timing signal generation circuit for generating a pulse and a vertical interpolation coefficient used for scanning line conversion linking with said timing signal generation circuit; and an interpolation circuit for interpolating a signal from the outputs of said first and second delay devices according to the output of said timing signal generation circuit.
Claim 13
Dependent Claim
194 words
A pixel conversion apparatus comprising: a sync separation circuit for separating a horizontal sync signal and a vertical sync signal from an input video signal; a field discrimination circuit for discriminating a field parity of said input video signal; a scanning line conversion circuit for converting the number of scanning lines of said input video signal; a first delay device for delaying the output of said scanning line conversion circuit by one horizontal period; a second delay device for delaying the output of said delay device by one horizontal period; a sync signal generation circuit for generating horizontal and vertical sync signals after conversion from the output of said sync separation circuit; a timing signal generation circuit for generating a pulse and a vertical interpolation coefficient used for scanning line conversion linking with said timing signal generation circuit; an interpolation circuit for interpolating a signal from the outputs of said first and second delay devices according to the output of said timing signal generation circuit; and a control circuit for controlling a reset signal of said sync signal generation circuit and said timing signal generation circuit according to the kind of input video signal.
Claim 14
Dependent Claim
216 words
A pixel conversion apparatus comprising: a sync separation circuit for separating a horizontal sync signal and a vertical sync signal from an input video signal; a field discrimination circuit for discriminating a field parity of said inpit video signal; a scanning line conversion circuit for converting the number of scanning lines of said onput video signal; a first delay device for delaying the output of said scanning line conversion circuit by one horizontal period; a second delay device for delaying the output of said delay device by one horizontal period; a sync signal generation circuit for generating horizontal and vertical sync signals after conversion from the output of said sync separation circuit; an interlace discrimination circuit for discriminating which the kind of input video signal is interlaced or non-interlaced; a timing signal generation circuit for generating a pulse and a vertical interpolation coefficient used for scanning line conversion linking with said timing signal generation circuit and said interlace discrimination circuit; an interpolation circuit for interpolating a signal from the outputs of said first and second delay devices according to the output of said timing signal generation circuit; and a control circuit for controlling a reset signal of said sync signal generation circuit and said timing signal generation circuit according to a kind of input video signal.
Claim 15
Dependent Claim
240 words
A pixel conversion apparatus comprising: a sync separation circuit for separating a horizontal sync signal and a vertical sync signal from an input video signal a field discrimination circuit for discriminating a field parity of said inpit video signal; a scanning line conversion circuit for converting the number of scanning lines of said onput video signal; a first delay device for delaying the output of said scanning line conversion circuit by one horizontal period; a second delay device for delaying the output of said delay device by one horizontal period; a sync signal generation circuit for generating horizontal and vertical sync signals after conversion from the output of said sync separation circuit; an interlace discrimination circuit for discriminating which the kind of input video signal is interlaced or non-interlaced; a timing signal generation circuit for generating a pulse and a vertical interpolation coefficient used for scanning line conversion linking with said timing signal generation circuit and said interlace discrimination circuit; an interpolation circuit for interpolating a signal from the outputs of said first and second delay devices according to the output of said timing signal generation circuit; a control circuit for controlling a reset signal of said sync signal generation circuit and said timing signal generation circuit according to a kind of input video signal; and a function which can forcibly initialize the various kinds of pulses outputted from said sync signal generation circuit and said timing signal generation circuit.
Claim 16
Dependent Claim
250 words
A pixel conversion apparatus comprising: pixel conversion means for converting the number of pixels from an input video signal; sync separation means for separating sync signals from said video signal; first and second dividers for dividing the frequencies of the horizontal and vertical sync signals separated at said sync separation means, respectively; means inputting the outputs of said first and second dividers and calculating the values of exclusive-OR; first and second PLL circuits; wherein said first PLL circuit comprises: first phase comparation means for comparing the signal phase by receiving the output of said sync separation means; first conversion means receiving the output of said first phase comparation means, converting the output into a dc voltage and deciding a response characteristic of the PLL; a first VCO for outputting a clock by the output of said first conversion means; a first counter for dividing the clock of said first VCO; and said second PLL circuit comprises: second phase comparation means for comparing the signal phase by receiving the output of said first counter; adding means receiving the output of said second phase comparation means and the output of said means calculating the values of exclusive-OR and adding the outputs; second conversion means receiving the output of said adding means, converting the output into a dc voltage and deciding a response characteristic of the PLL; a second VCO for outputting a clock by the output of said second conversion means; a second counter for dividing the clock of said second VCO.
Claim 17
Dependent Claim
62 words
A pixel conversion apparatus, wherein in a picture display apparatus providing with a plurality of PLL circuits and digitally processing a video signal so as to convert the number of pixels by a plurality of clocks having each different period, a signal having a specific period is added to a phase comparison detection value of one of said plurality of PLL circuits.
Claim 18
Dependent Claim
76 words
A pixel conversion apparatus, wherein in order to convert the number of pixels per one horizontal period of an input video signal into the desired number of pixels, the number of horizontal pixels is increased by using a clock having a higher frequency than a clock generating said video signal as a sampling clock of an A/D converter and the number of pixels is converted into the desired number of pixels, processing interpolation between the pixels.
Claim 19
Dependent Claim
101 words
A pixel conversion apparatus comprising: a PLL circuit for generating a clock locking to a horizontal sync signal with a higher frequency than a clock generating the input video signal; an A/D converter for converting said input video signal into a digital signal by a clock from said PLL circuit; a memory for storing pixel data during a horizontal period; interpolation means being put between said A/D converter and said memory and interpolating between the adjacent pixels; control means for generating write control signal to control writing in said memory, in order to make the number of pixels a desired number.
Claim 20
Dependent Claim
44 words
A pixel conversion apparatus as recited in claim 19 further comprising: a high frequency band enforcing circuit connected to the previous stage of interpolation means, in order to previously compensate the high frequency band of the video signal detriorated by interpolation processing between pixels.
Claim 21
Dependent Claim
48 words
A pixel conversion apparatus as recited in claim 19 further comprising: a counter generating an initializing signal to initialize interpolation means at every numerator of a reduced fraction making the desired number of pixels as a denominator, taking the number of pixels after A/D conversion as a numerator.
References Cited (Backward Citations)
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